Papers by Keyword: Gate Oxide Integrity

Abstract: In this paper, 1.2 kV SiC trench MOSFET with deep P structure has been proposed to effectively shield the trench bottom oxide. The various design splits, such as N concentration between deep P and deep P to trench distance, were experimentally evaluated and TCAD simulations were performed to extract maximum oxide electric field at trench bottom. Based on trade off results, critical design parameters were optimized to obtain low Rdson and stable breakdown voltage with acceptable oxide electric field. To evaluate trench gate oxide reliability in wafer level, gate oxide integrity (GOI/Vramp), charge to breakdown (QBD), and time dependent dielectric breakdown (TDDB) tests were conducted. Also, high temperature gate bias (HTGB) and high temperature reverse bias (HTRB) stress tests were carried out for assembled samples to compare device reliability depending on different designs. For the target design, the promising reliability results were confirmed in both wafer level and assembled samples.

Abstract: The static electricity of wet clean was characterized by contactless surface voltage measurement on silicon oxide dielectric in this study. The paper shows surface static charge at wafer center caused by a single wafer spin cleaning tool. Deionized water (DIW) rinse was verified as the critical step of inducing static charge. It was demonstrated by metal oxide semiconductor (MOS) capacitor that such serious dielectric static charge would degrade gate oxide integrity (GOI). With dissolved CO₂ to lower DIW resistance, surface static charge at wafer center is reduced and degraded GOI is restored as a result.