Papers by Keyword: Graphite Cap

Abstract: The effects of using a graphite capping layer during implant activation anneal on the performance of 4H-SiC MOSFETs has been evaluated. Two sets of samples, one with the graphite cap and another without, with a gate oxide process consisting of a low-temperature deposited oxide followed by NO anneal at 1175°C for 2hrs were used for characterization. Various device parameters, particularly threshold voltage, subthreshold slope, field-effect mobility, inversion sheet carrier concentration and Hall mobility have been extracted for the two processes.

Abstract: N+ 4H-SiC commercial substrates with n-type epilayers have been used to realize bipolar diodes and TLM structures. The p-type emitter of diodes was realized by Al implantations followed by a post-implantation annealing with or without a graphite capping layer. Ohmic contacts were formed by depositing Ti/Ni on the backside and Ni/Al on the topside of the wafer. It appears that capping the sample during the annealing reduces considerably the surface roughness and the specific contact resistance. Sheet resistance and specific contact resistance as low as 2kΩ/□ and respectively 1.75×10-4 Ωcm² at 300 K have been obtained. I-V measurements as a function of temperature have been performed from ~100 to ~500 K. The variations of the series resistance vs. temperature can be explained by the freeze-out of carriers and by the variation of carrier mobility.

Abstract: 6H and 4H–SiC epilayers were Al-implanted at room temperature with multiple energies (ranging from 25 to 300 keV) in order to form p-type layers with an Al plateau concentration of 4.5×1019 cm-3 and 9×1019 cm-3. Post-implantation annealing were performed at 1700 or 1800 °C up to 30 min in Ar ambient. During this process, some samples were encapsulated with a graphite (C) cap obtained by thermal conversion of a spin-coated AZ5214E photoresist. From Atomic Force Microscope measurements, the roughness is found to increase drastically with annealing temperature for unprotected samples while the C capped samples show a preservation of their surface states even for the highest annealing temperature. After 1800°C/30 min annealing, the RMS roughness is 0.46 nm for the lower fluence implanted samples, slightly higher than for unimplanted samples (0.31 nm). Secondary Ion Mass Spectroscopy measurements confirm that the C cap was totally removed from the SiC surface. The total Al-implanted fluence is preserved during postimplantation annealing. A redistribution of the Al dopants is observed at the surface which might be attributed to Si vacancy-enhanced diffusion. An accumulation peak is also observed after annealing at 0.29 9m, depth corresponding to the amorphous/crystalline interface that was determined on the as-implanted samples by Rutherford Backscattering Spectroscopy in channeling mode. The redistribution of the dopants has an impact on their electrical activation. A lower sheet resistance (Rsh= 8 k
) is obtained for samples annealed without capping than for samples annealed with C capping (Rsh= 15 k
).

Abstract: Low resistance p-layers are achieved in this paper using a graphite cap to protect SiC surface from out-diffusion of Si during high temperature post-implantation annealing, which is carried out to maximize the activation of Al dopant in 4H-SiC. With a graphite layer converted from photoresist, as high as 1700 and 1800oC post-implantation annealing is able to be used. Low RMS roughness of surface after high temperature annealing shows the effectiveness of the graphite cap. Small sheet resistance and resistivity are also achieved from the high temperature annealing. At room temperature, sheet resistances of 9.8 and 1.3 k
/□, and the corresponding resistivities of 235 and 31 m
-cm are obtained from 1700 and 1800oC annealed samples, respectively. The Al ionization energy extracted from Arrhenius plot is also close to the typical reported values. Therefore, it can be concluded that, using graphite cap could help to activate the Al dopant effectively during high temperature annealing.

Abstract: Results of a 1200V 4H-SiC vertical DMOSFET based on ion implanted n+ source and pwell regions are reported. The implanted regions are activated by way of a high temperature anneal (1675°C for 30 min) during which the SiC surface is protected by a layer of graphite. Atomic force microscopy shows the graphite to effectively prevent surface roughening that otherwise occurs when no capping layer is used. MOSFETs are demonstrated using the graphite capped anneal process with a gate oxide grown in N2O and show specific on-resistance of 64 mW×cm2, blocking voltage of up to 1600V and leakage current of 0.5–3 ´10-6 A/cm2 at 1200V. The effective nchannel mobility was found to be 1.5 cm2/V×s at room temperature and increases as temperature increases (2.8 cm2/V×s at 200°C).

Abstract: Technological aspects of ion implantation in SiC device processes are described. Annealing techniques to suppress surface roughening of implanted SiC (0001) are demonstrated. Trials to achieve a low sheet resistance are described for n-type and p-type doping. Implantation into the (11-20) face is also presented. Electrical behaviors of implants near implanted tail regions are discussed based on experiments.