Papers by Keyword: High-K Dielectric

Abstract: Strontium titanate SrTiO₃ thin films have been fabricated by radio frequency magnetron sputtering on P-type Si at substrate temperature of 200°C. Two different postdeposition annealing methods were applied on the sputtered films. Specifically, conventional thermal annealing at 300°C for 60 min and photoactivation treatment under deep ultraviolet-ozone for 30 min. The dielectric properties of the SrTiO₃ thin films were investigated by fabricating Au/STO/p-Si MOS capacitors. A dielectric constant (κ) with a value of 13 was obtained for as-deposited film, which has a thickness of 107 nm. While post-annealed samples showed elevated values of κ, precisely, 15.33 and 19.32 for films exposed to deep ultraviolet-ozone photoactivation and films annealed at 300°C, respectively. All devices showed a leakage current in the order of 10^-8 A/cm² at 1V. Based on XPS analysis, photo-activated films revealed the lowest percentage of oxygen vacancies, which designates the capability of this technique to enhancing films quality at a lower temperature.

Abstract: The Indium Gallium Arsenide (InGaAs) based MOSFETs have been widely used in the research of high-speed devices with higher frequency. It has some application in the designing areas of power amplifiers. The InGaAs mainly have greater electron mobility and the lesser band gap in their compound makes them more suitable for developing high-speed devices. The Indium Gallium Arsenide compound-based MOSFETs are designed using the source/drain grown on a passive layer of Indium Phosphide substrate. This helps in reducing the power budget of the MOSFET and thereby reduces source and drain resistance. The re-grown layers over the bulk have serious issues such as parasitic capacitance and greater electrical field at the terminals of the gate along with the drain terminal. This results in a larger leakage current along with the terminals and thereby induces the degradation of the frequency of the application amplifiers. The high-ƙ dielectric along the gate terminal makes the device immune to leakage current for lesser frequency applications. The optimum material for the dielectric may be Hafnium (IV) Oxide – HfO₂ which has been used as a sidewall in the proposed InGaAs MOSFET design. The device simulation was carried out in a way to evaluate the characteristics of the proposed designs. The results were submissive to the conventional MOSFETs in terms of output capacitance over the source and drain terminals, leakage current in the drain terminal, and improved frequency parameters. The results also suggested that the sidewall design over the gate terminal constitutes the frequency improvement without losing the power and current characteristics.

Abstract: The channel material of a gate describes the operating condition of the MOSFET. A suitable operating condition prevails in MOSFETs if the transistors are quite enough to observe and control at the nanometer regime. An efficient gate and channel material have been proposed in this work which is based on the electrical properties they exhibit at the temperature of 300 K. The doping concentration for the electrons and holes is maintained to be 1Χ10¹⁹cm^-3 for the entire electronic simulator. The simulation results show that using La₂O₃ along with Indium Nitride (InN) material for the designing of Double-Gate (DG) MOSFETs provides better controllability over the transistor at a channel length of 50 nm. This proposed DG-MOSFET is more compliant than the conventional coplanar MOSFETs based on Silicon.

Abstract: We report on a novel method of stacking multiple oxide layers on 4H-SiC 20 kV IGBT. Instead of SiO₂/SiC interface which is common for any SiC based MOS device, we found that the AlN/SiC interface would yield better results. We have performed 2D numerical simulations to analyze static characteristics for three combinations of dielectric stacks on IGBT: HfO₂-SiO₂, HfO₂-AlN, and HfO₂-SiO₂-AlN (by maintaining the same equivalent oxide thickness value). In addition to higher transconductance (g_m) and lower subthreshold swing (SS), the device with AlN/SiC interface offer comparatively lower R_SP,ON and higher mobility with respect to temperature. Nevertheless, with a partial compromise on device characteristics improvement, insertion of SiO₂ in the dielectric stack helps in suppressing the subthreshold current owing to higher band offset with respect to SiC. The turn off characteristics of the device is analysed using a clamped inductive circuit. Device with AlN/SiC has shown better dI_c/dt and fall time compared to SiO₂/SiC interface.

Abstract: This paper deals with investigation and fabrication of 4H-SiC MOSFETs with a high-k dielectric close to ZrSiO₄. We are looking for the optimal stochiometry in order to obtain full benefits of its large bandgap, a k value higher than that of SiO₂, thermodynamic stability on SiC, a good interface quality and process compatibility with SiC technology. Several Si/Zr ratios have been tested with the purpose of obtaining the most favorable dielectric configuration. The first test devices have been manufactured successfully with a stack gate dielectric consisting of a thin SiO₂ interlayer and a Zr_xSi_yO_z (theoretical Si/Z=0.7) layer on top.

Abstract: This paper proposes a new structure of 4H-SiC bipolar junction transistor, which can both achieve high current gain and high open base breakdown voltage. By introducing a groove type of metal-high k dielectric-silicon carbide (MIS) structure into the active region along the base-emitter sidewall which is formed with the process of isolation etching, a large electric field appears at the interface between high-k dielectric and bulk material by analyzing the potential distribution in forward mode, thus accelerating the electron transport. Based on a doping concentration of 4×10¹⁷cm^-3 and thickness of 0.6um base region, current gain of as high as 191 is obtained using TCAD simulation, and that is almost double of the conventional structure in the same simulation setup. Furthermore, a field plate structure is composed combined with the base contact metal simultaneously, and the open base breakdown voltage is obviously increased from 634V to 948V with a 6μm-thick n-SiC collector (N_d=3×10¹⁵cm^-3).

Abstract: Exposing the Early effect (or called channel-length modulation effect) at deep subnano node high-k/metal gate (HK/MG) process is still beneficial to IC designers to reduce the obsession in design. This effect contributes the operating point in circuit concern and process adjustment. For the long channel device, the intercept under various gate voltages focuses on one point consistent with conventional device. However, the divergent phenomenon was observed at the short channel tested device due to the higher strain effect, causing the non-uniform electrical field distribution in channel.

Abstract: The potential impact of high permittivity gate dielectrics on the performance of a ballistic nanoscale CNTFET is studied over a wide range of dielectric permittivities with low temperatures ranging from room temperature down to 100 K. Using the non-equilibrium Greens function (NEGF) formalism. Device characteristics such as I_ON/I_OFF current ratio, threshold voltage, the drain induced barrier lowering (DIBL). The effects of temperature varying are also examined.

Abstract: RF characteristics of metal-insulator-metal (MIM) capacitors with SiO2/HfO2/SiO2 (SHS) were investigated using an equivalent circuit model that is associated with the main impedance ZMIM.cap and the substrate-related conductance Ysub. However, the parasitic capacitance in Ysub was lower than that of another element component in ZMIM.cap, which makes difficult for accurate RF modeling because the parasitic component was dominant at high frequency regions. As low parasitic component is eliminated from the modeling, the extracted capacitance for SHS MIM capacitor was stable up to 20 GHz. The Q-factor and resonant frequency (fr) point of SHS structure are 23.9 at 1 GHz and 9.76 GHz, respectively.

Abstract: Issues such as Tunneling, Leakage Currents and Light-Atom Penetration through the Film Are Threatening the Viability of Ultra-Thin Sio₂ as a Good Dielectric for Industrial and Electronic Devices and in Ceramic Technologies. in this Paper, the Effect of Zirconium-Doped Lanthanum Oxide Is Investigated in the Hope that this Material Can Be Used as a Good Gate Dielectric for the next Generation of CMOS (Complementary-Metal-Oxide-Semiconductor). Zirconium Lanthanum Oxide Nanocrystallites with General Formula of Zr_xla_1-xO_y Were Prepared by Using the Sol-Gel Method, such that the Zr Atomic Fractions in the Material Were in the Range of X = 5%, 20% and 50%. the Nanocrystallite’s Phases and Properties Were Characterized Using X-Ray Diffraction (XRD), Scanning Electron Microscopy (SEM) and Atomic Force Microscopy (AFM) Techniques. Electrical Property Characterization Was Also Performed Using the Cyclic-Voltameter (C-V) Technique in TRIS Solution (pH = 7.3). C-V Measurements Show that Current through the TRIS Reduces at Higher Temperatures. Moreover, Elemental Qualitative Analysis Was Performed via Energy Dispersive X-Ray (EDX) Spectroscopy and Confirmed the above Claims.