Papers by Keyword: High Speed

Abstract: We carried out chemical mechanical polishing (CMP) on commercially available 6 inch SiC wafers (epi-ready products) with slurries containing different abrasive types and evaluated the latent scratch density from the mapping measurement of the wafers using mirror projection electron microscope (MPJ). Comparing to the wafer before polishing, the latent scratch density decreased on the wafer polished with MnO₂+KMnO₄, while that increased by polishing with Al₂O₃+KMnO₄. The two-step polishing using first Al₂O₃+KMnO₄ and then SiO₂+H₂O₂ can reduce the latent scratch density to the same level as that with MnO₂+KMnO₄, but long polishing time is required because of the low polishing rate in the process with SiO₂+H₂O₂. We investigated the reason why MnO₂ slurry can suppress the occurrence of latent scratches by a polishing test on a wafer with an SiO₂ film on its (0001)Si surface. The results suggest the oxidation of the SiC surface is rate-determining step for polishing with MnO₂+KMnO₄. It was also found that wafers without an SiO₂ film could not be polished with only MnO₂ abrasives. Thus the mechanical contribution to polishing by MnO₂ abrasives in KMnO₄-based slurry is smaller than the chemical contribution, which can suppress the occurrence of latent scratches. KMnO₄-based slurry containing MnO₂ abrasives performs the CMP process with low latent scratch density in a time shorter than that containing Al₂O₃ or SiO₂ abrasives.

Abstract: As a key part of the RF PA system, VRM (Voltage-Regulate-Modulator), whose main role is to offer pulse voltage for RF power transistor, is often slighted. As a result, VRM has been a restraining factor now. In order to realize the needs of high speed and high frequency, a new method based on enhancement mode GaN HEMT of designing VRM is proposed in this paper. By using this method, the rise time and fall time of VRM could be as about 10ns with the peak voltage 75V and the peak current 150A, which is quite suitable for driving high voltage and high power GaN-based RF power transistor.

Abstract: The increasing demand for electronics in harsh environment applications has inspired investigation of silicon carbide (SiC)-based devices and circuits, due to its superior electrical properties. Several researchers have demonstrated the viability of 4H-SiC control circuitry by developing small scale logic circuits entirely in 4H-SiC. However, development and design of memory elements, which is a critical component in any electronic system, is still not fully explored. To bridge this gap, this paper presents, a complete bipolar, static random access memory (SRAM) column that includes the memory cell and the peripheral circuitry, designed to exploit the unique properties of SiC. Simulation results for the proposed memory show stable operation across a wide range of temperatures (27 °C – 500 °C) with good noise margins and access speeds while running at a supply voltage as low as 5 V. This work validates the potential of developing memory architectures in 4H-SiC, paving the way for realizing small-sized digital systems for harsh environments.

Abstract: To study the mechanism of metal cutting deformation, we invented a new type of explosion rotary quick-off tools test device which was based on absorbing advantages of existing cutting deformation test device. So that the tool can be separated from the workpiece with a larger acceleration and the complete chip root samples can be obtained. This new type of explosion rotary quick-off tools test device composed of foundation, explosion chamber, piston body, pressure plate, locking wedge and customized tools, which has many advantages such as simple structure, convenient operation and high rigidity.

Abstract: We report the development of two epilayers namely the baseline highly strained channel and enhanced low gate leakage samples. The Hall data shows that the enhanced epilayer portraying higher sheet carrier concentration, but comparable carrier mobility in the 2-DEG layer, as compared to the baseline sample. The WinGreen simulation also conformed the enhanced epilayer advantages where wider Schottky barrier is observed and subsequently double carrier concentration is simulated in the channel. Both samples show low AuGe/Au Ohmic contact resistivity of approximately 0.16 Ω.mm. A tremendous advantage on 1 μm Schottky gate leakage is also recorded on enhanced epilayer where the leakage is more than seven times lower than that of the baseline sample. The resulted characteristics are much better than the reported submicron device, thus this device has find an important application in high-gain lossless transmission, especially in underwater optical communication system.

Abstract: The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

Abstract: One of the significant characteristics in machining process is final quality of surface. The best measurement for this quality is the surface roughness. Therefore, estimating the surface roughness before the machining is a serious matter. The aim of this research is to estimate and simulate the average surface roughness (Ra) in high speed end milling. An experimental work was conducted to measure the surface roughness. A set of experimental runs based on box behnken design was conducted to machine carbon steel using coated carbide inserts. Moreover, the Adaptive Neuro-Fuzzy Inference System (ANFIS) has been used as one of the unconventional methods to develop a model that can predict the surface roughness. The adaptive-network-based fuzzy inference system (ANFIS) was found to be capable of high accuracy predictions for surface roughness within the range of the research boundaries.

Abstract: In this paper, low power and high speed D-latch and nand gates (as sample of combinational and sequential circuits) are designed based on cnfet and cmos technology. The performance of D-latch and nand is compared in two technologies of 65nm and 90nm in cmos and cnfet technology. The circuit designs are simulated using hspice. Finally, the power consumption and delay and pdp as well as rise and fall time are compared in various voltages and frequencies. The results show that cnfetD-latch and nand gates have better delay and power consumption in comparison to cmos technology.

Abstract: A ball-screw system is widely used in high speed transmission platforms. High transmission speed brings high frictional force, heat and thermal expansion occurring on contact areas of ball, screw and nut. Positioning error of platform is affected by the thermal expansion during linear transmission. A vertical motion of ball-screw driving system was used for high speed transmission test. Thermal expansion of screw and positioning error were measured for discussion their effects. Cyclic vertical motion during a long transmission distance, 2 km, will integrate thermal heat to ball, screw and nut, thermal expansion of screw is also occurred. From experiments, temperature rising and thermal expansion of screw and nut were recorded and calculated for estimate elongation and positioning error of a vertical motion high speed ball-screw. Positioning error is not totally respected thermal elongation effects of screw and nut owing to contact forces caused by wear and thermal expansion at contact areas comparing to the heavy axial load is relative small in a vertical motion ball-screw system. Therefore, the structure stiffness is not affected significantly by thermal effect and wear.

Abstract: With the rising of public environmental awareness and energy saving goal, high efficient transmission of ballscrew is widely used for production equipment. Of all the ballscrew application, heavy loading is the most stringent operation condition. The crucial techniques for this application are ball recirculation system and lubrication design. In this article, a heavy-load type ballscrew is verified to meet the application requirements through experiments, dynamic simulations and test runs on test bench.