Papers by Keyword: High Voltage

Abstract: The aim of this study is to investigate the main contributing factors to the degradation of the intrinsic body diode in SiC MOSFETs, caused by the expansion of stacking faults (SFs) from the substrate into the epitaxial layer, and how it affects their performance. Additionally, a comparison between DC forward current stress and surge current pulse stress is shown.

Abstract: This work addresses the electrical behaviour of high-voltage (HV) SiC MOSFETs, being the main motivation to check their robustness. Large area (25 mm²) devices rated for 3.3 kV applications were fabricated with a special process for the gate oxide formation. The unit cell was designed to achieve good short-circuit performance. Static and dynamic characterization is presented at room and high temperature. Output curves and 3^rd quadrant behaviour were analysed. Dynamic tests were performed at high bus voltages and high current. To check device robustness, short-circuit and power cycling’s were considered. Robustness test results put in evidence the achievement of reasonable good results obtained due to a suitable cell design.

Abstract: In this paper, the structural cell design optimization of 15kV 4H-SiC p-channel IGBT is performed. The effects of the parameters of JFET region on the blocking voltage and the forward characteristics are analyzed by numerical simulations. The results indicate that the JFET width and JFET region concentration have an important effect on the performance of IGBTs. Based on the simulation structure in this paper, the optimum JFET width is 10μm, and the optimum JFET concentration is 7×10¹⁵cm⁻³. Meanwhile, they should be carefully designed to achieve the best trade-off between the blocking voltage and the forward voltage drop.

Abstract: High performance 15 kV n-GTOs were demonstrated for the first time in 4H-SiC. The device utilized a 140 μm thick, lightly doped n-type drift layer, with 1450°C lifetime enhancement oxidation, which resulted in a carrier lifetime of 17.5 μs. The p⁺ backside injector layer was thinned to minimize parasitic resistances. A room temperature forward voltage drop of 5.18 V was observed at a current density of 100A/cm². A 1 cm² device showed a leakage current of 0.17 μA at 15 kV. The 4H-SiC n-GTO showed latching characteristics, and showed a turn-off time of 170 ns in a resistive load switching setup, which represents about a factor of 45 improvement in turn-off speed over 4H-SiC p-GTOs with comparable voltage and current ratings.

Abstract: To address stringent performance and reliability requirements of industrial and traction power conversion systems we have developed planar 3,300V MOSFETs at a 6-inch SiC-compatible silicon CMOS foundry. By optimizing the unit cell structure and using a deep current-spreading layer we demonstrated a low MOSFET specific on-resistance R_DSA=11.2 mΩ·cm² (I_D=5A, V_GS=15V) and fast switching for the baseline design. Robust short-circuit handling (7.5μs at Vds=1500V and 5.0μs at Vds=2200V) was demonstrated with an alternative unit cell design with R_DSA=14.8 mΩ·cm² (I_D=5A, V_GS=15V).

Abstract: In this paper, we present our latest results on 650 V 4H-SiC DMOSFET developments for dual-side sintered power modules in electric drive vehicles. A low specific on-resistance (R_sp,on) of 1.8 mΩ⋅cm² has been achieved on 650 V, 7 mΩ 4H-SiC DMOSFETs at 25°C, which increases to 2.4 mΩ⋅cm² at 150°C. For the first time, the DMOSFET chip is designed specifically for use in dual-side soldering and sintering processes, and a 650 V, 1.7 mΩ SiC DMOSFET multichip half bridge power module has been built using the wirebond-free assembly. Compared to a similarly rated Si IGBT module, the conduction and switching losses were reduced by 80% and ~50%, respectively.

Abstract: An investigation into the increased leakage currents and reduced blocking voltages associated with 1450°C lifetime enhancement oxidation for the 4H-SiC p-GTOs is presented. Roughening of the 4H-SiC surface due to localized crystallization of SiO₂, or crystobalite formation, during the high temperature oxidation was identified as one of the main causes of this issue. A factor of 30 difference in permeability to O₂ between amorphous SiO₂ and crystobalite caused uneven oxidation, which resulted in significant roughness. This roughness, placed at the metallurgical junction between the gate and the drift layer, where the E-field is greatest, is believed to be responsible for the premature breakdown characteristics. A 2-step lifetime enhancement process, which moves this roughness to the lower E-field region of the device was introduced to alleviate this issue. A 15 kV 4H-SiC p-GTO with the 2-step lifetime enhancement process demonstrated a significant reduction in V_F over the 1300°C oxidized devices, without any impact on blocking characteristics.

Abstract: 1.2 kV SiC buried grid junction barrier Schottky (BG-JBS) diodes are demonstrated. The design considerations for high temperature applications are investigated. The design is optimized in terms of doping concentration and thickness of the epilayers, as well as grid size and spacing dimensions, in order to obtain low on-resistance and reasonable leakage current even at high temperatures. The device behavior at temperatures ranging from 25 to 225^ºC is analyzed and measured on wafer level. At 100 A/cm² a forward voltage drop of 2 V at 25^ºC and 3 V at 225^ºC is achieved. At reverse voltage of 1 kV, a leakage current density below 0.1 µA/cm² and below 0.1 mA/cm² is measured at 25 and 225^ºC, respectively. This proves the effective shielding effect of the BG-JBS design and provides benefits in high voltage applications, particularly for high temperature operation.

Abstract: This paper presents an overview of the main technical requirements of high voltage Silicon Carbide MOSFETs rated above 3300V when compared to the well-established requirements of Silicon IGBTs and diodes. Combined with a performance evaluation of existing 3300 V SiC MOSFET prototypes from ROHM, the paper will discuss the benefits and challenges facing these devices for targeting mainstream and future topologies employed in high power applications such as those in grid systems, railway traction and industrial drives. The paper will also attempt to provide an outlook into potential development trends towards exploiting the full benefits of SiC MOSFETs.

Abstract: Due to their fast switching speed, knee-free forward characteristics, and a robust, low reverse recovery body diode, SiC MOSFETs are ideal candidates to replace silicon IGBTs in many high-power medium-voltage applications. 1700 V SiC MOSFETs have already been released to production at Wolfspeed based on its 2^nd Gen technology. In this paper, we present our latest results in high voltage 4H-SiC MOSFET development. A low specific on-resistance of 4.7 mΩ⋅cm² has been achieved on 1700 V, 20 mΩ 4H-SiC DMOSFETs at 250°C based on a 3^rd generation planar MOSFET platform, which is less than half of the resistance of the previous generation devices. A detailed analysis has been carried out with respect to the static and dynamic characteristics, third quadrant conduction, and body diode reverse recovery charge, etc.