Papers by Keyword: High Voltage (HV)

Abstract: This work is focused on the 0.25 μm 60 V high-voltage pLDMOS deviceswhich will be integrated with an FOD structure in the bulk region, and its ESD protection ability is improved by using this architecture. It is found that as an FOD element adding, the FOD area ratio is increased, I_t2 value will be enhanced too. However, as the FOD area ratio is increased, the V_t1 value of thecorresponding sample is not changed so much about a range of 1 ~ 2V; at thesame time the R_on value will be declined, which were due to a uniformconduction phenomenon. From the experimental data,it is revealed that the I_t2value improved 15.4%, and R_on valuedecreased about 8.6%.

Abstract: A growing demand for smart and flexible photovoltaic power conversion and pulsed-power systems is leading to rapid development and commercialization of medium voltage 6.5 - 24 kV, wide-bang gap rectifiers and switches. Conventional silicon bipolar switches are limited to roughly 8 kV breakdown voltages and scaling up the voltage rating requires very thick wafers presenting significant manufacturing challenges. Very thick drift layers of silicon devices also translate into a very high minority carrier charge injected during forward conduction for an efficient conductivity modulation, hence leading to an extremely slow switching speed and poor efficiency. In this paper USCi presents the development of 6.5 kV 4H-SiC gate-turn-off thyristors (GTOs) with multiple floating guard-ring edge termination, and describes their application in an AC-link grid-tied solar inverter system.

Abstract: 13-kV 4H-SiC PiN diodes were fabricated on 4° and 8° off-axis substrates and their electrical properties were examined. Small test PiN diodes with various JTE concentrations were fabricated and the dependence of JTE concentration was examined. The highest breakdown voltages were 14.6 and 14.1 kV at a JTE1 concentration of 1.9 × 10¹⁷ cm⁻³ for both the 4° and 8° off-axis substrates. Based on the results, 4 mm × 4 mm SiC PiN diodes were successfully fabricated and exhibited avalanche breakdown voltages of 14.0 and 13.5 kV for the 4° and 8° off-axis substrates, respectively. Forward voltage degradation was larger for the 8° off-axis substrates.

Abstract: The multiple-zone junction termination extension (MJTE) is a widely used SiC edge termination technique that reduces sensitivity to implantation dose variations. It is typically implemented in multiple lithography and implantation events. To reduce process complexity, cycle time, and cost, a single photolithography/implantation (P/I) MJTE technique was developed and diodes with 3-zone and 120-zone JTEs were fabricated on the same wafer. Here, the process tolerance of the single (P/I) MJTE technique is evaluated by performing CCD monitored blocking voltage measurements on diodes from the same wafer with the 3-zone and 120-zone single (P/I) JTE. The 3-zone JTE diodes exhibited catastrophic localized avalanches at the interface between the 2nd and 3rd zones due to abrupt zone transitions. Diodes with the smooth transitioning 120-zone JTE exhibited no CCD detectable avalanches in their JTE regions up to the testing limit of 12 kV. Under thick dielectric (deposited for on-wafer diode interconnection), diodes with the single P/I 3-zone JTE failed due to significant loss of high-voltage capability, while their 120-zone JTE diode counterparts were minimally affected. Overall, the single (P/I) 120-zone JTE provides a process-tolerant and robust single P/I edge termination at no additional fabrication labor.

Abstract: In this work, we report our recently developed 16 kV, 1 cm², 4H-SiC PiN diode results. The SiC PiN diode was built on a 120 µm, 2×10¹⁴/cm³ doped n-type SiC drift layer with a device active area of 0.5175 cm². Forward conduction of the PiN diode was characterized at temperatures from 20°C to 200°C. At high injection-current density (J_F) of 350 ~ 400 A/cm², the differential on-resistance (R_ON,diff) of the SiC PiN diode decreased from 6.08 mΩ·cm² at 20°C to 5.12 mΩ·cm² at 200°C, resulting in a very small average temperature coefficient of –5.33 µΩ·cm²/°C, while the forward voltage drop (V_F) at 100 A/cm² reduced from 4.77 V at 20°C to 4.17 V at 200°C. This is due to an increasing high-level carrier lifetime with an increase in temperature, resulting in reduced forward voltage drop. We also observed lower R_ON,diff at higher injection-current densities, suggesting that a higher carrier lifetime is needed in this lightly doped n-type SiC thick epi-layer in order to achieve full conductivity modulation. The anode to cathode reverse blocking leakage current was measured as 0.9 µA at 16 kV at room temperature.

Abstract: In this paper, we report our recently developed 1 cm², 15 kV SiC p-GTO with an extremely low differential on-resistance (_RON,diff) of 4.08 mΩ•cm² at a high injection-current density (J_AK) of 600 ~ 710 A/cm². The 15 kV SiC p-GTO was built on a 120 μm, 2×10¹⁴/cm³ doped p-type SiC drift layer with a device active area of 0.521 cm². Forward conduction of the 15 kV SiC p-GTO was characterized at 20°C and 200°C. Over this temperature range, the R_ON,diff at J_AK of 600 ~ 710 A/cm² decreased from 4.08 mΩ•cm² at 20°C to 3.45 mΩ•cm² at J_AK of 600 ~ 680 A/cm² at 200°C. The gate to cathode blocking voltage (V_GK) was measured using a customized high-voltage test set-up. The leakage current at a V_GK of 15 kV were measured 0.25 µA and 0.41 µA at 20°C and 200°C respectively.

Abstract: The latest developments in ultra high voltage 4H-SiC IGBTs are presented. A 4H-SiC P-IGBT, with a chip size of 8.4 mm x 8.4 mm and an active area of 0.32 cm², which is double the active area of the previously reported devices [1], exhibited a blocking voltage of 15 kV, while showing a room temperature differential specific on-resistance of 41 mΩ-cm² with a gate bias of -20 V. A 4H-SiC N-IGBT with the same area showed a blocking voltage of 17 kV, and demonstrated a room temperature differential specific on-resistance of 25.6 mΩ-cm² with a gate bias of 20 V. Field-Stop buffer layer design was used to control the charge injection from the backside. A comparison between N- and P- IGBTs, and the effects of different buffer designs, are presented.

Abstract: A necessity for the successful commercialization of SiC power devices is their long term reliability under the switching conditions encountered in the field. Normally-ON 1200 V SiC JFETs were stressed in repetitive hard-switching conditions to determine their fault handling capabilities. The switching pulses were generated from an RLC circuit, where energy initially stored in capacitors discharges through the JFET into a resistive load. The hard-switching included one million repetitive pulsed hard-switching events at 25 °C from a drain blocking-voltage of 600-V to an on-state current of 67 A, and an additional one million 600-V/63-A pulsed hard-switching events at 150 °C. The JFET conduction and blocking-voltage characteristics are virtually unchanged after over two million hard switching events proving the devices are reliable for handling high surge-current faults like those encountered in bidirectional circuit breaker applications.°

Abstract: The performance of a high-field asymmetric waveform ion mobility spectrometry (FAIMS) detector is directly related to the quality of the asymmetric waveform generator. In this paper, we propose a design scheme of a multi-mode asymmetric waveform generator based on the half-bridge architecture, using a direct digital synthesizer (DDS) method to produce a frequency adjustable square wave pulse and half-sine pulse signal. An isolation circuit was combined with a drive circuit through a TLP250 which is a MOSFET driver chip with photoelectric isolation. The frequency of the proposed waveform generator can be easily controlled.

Abstract: In an nLDMOS, both the drain-side and source-side engineering by adding N_ad and P_ad layers to obtain a weak snapback characteristic are presented in this work. In this paper, we will detailedly discuss the trigger voltage (V_t1) and holding voltage (V_h) distribution of a novel high-voltage (HV) nLDMOS device. It’s a novel method to reduce the V_t1 and to increase the V_h. Therefore, these efforts will be very suitable for the HV applications in power management ICs.