Papers by Keyword: IGBT

Abstract: The goal of this work is to use MATLABSimulink to create a simulation of a DC-to-DC boostconverter it, utilizing SPMC topology that is a matrixconverter with only one phase. With the outputboosted more than that the fluctuations are quiet high.In this project work, we have tried to boost up theoutput to five times after keeping the fluctuations aslow as possible. The output voltage is controlled usingthe PWM approach. IGBT is used in four pairs andtaken as the switching device. Four pairs of diodes arealso used with the IGBTs and are placed in parallel andopposite direction. The simulation was performed at aswitching frequency of 10 kHz, and the findings werein excellent agreement with the quadrant operation'sfirst quadrant, and it was able to increase the voltageof itsinput by about five times . In addition, an inverterissuccessfully created, demonstrating the use of matrixtopology.

Abstract: This work presents the design methodology and performance of a compact edge termination structure aiming 10kV+ rated Silicon Carbide (SiC) devices. Standard Floating Field Rings (FFRs) for such high voltage rating SiC devices are not favored because they are inefficient in terms of the achievable breakdown voltage as a percentage of the 1D maximum, consume large chip area, require high implantation energies and small gaps between rings which can violate fabrication limits. We show that the implantation of Aluminium at the bottom of carefully positioned trenches can be analogous to deep Aluminium implantation in terms of performance, thus annulling the need for small gaps between rings and MeV ion implantation. We optimize the distribution of trenches by placing them in multiple zones of different expansion coefficient. The proposed multi expansion ratio Trench FFR termination was utilized to terminate the active area of a 10kV rated Punch Through n-IGBT having 0.8 μm p-body and 100 μm, 3×10¹⁴ cm^-3 drift region. We found the 0.6–0.8 µm to be the most optimum trench depth, achieving over 10 kV within less than 500 μm of termination length.

Abstract: 6.5 kV SiC PiN diode with JTE and p+ rings termination was fabricated and characterized. The static and dynamic performance of SiC PiN diode were compared with that of SiC JBS diode and silicon diode, while switched in combination with a silicon IGBT. SiC PiN provides clear advantage while operating at higher current densities (above 100 A/cm²) and had lower leakage current. When switched together with a silicon IGBT, they contribute to losses similar to that of a SiC JBS diode.

Abstract: The commercial success of silicon carbide (SiC) diodes and MOSFETs for the automotive industry has led many in the field to begin developing ultra-high voltage (UHV) SiC insulated gate bipolar transistors (IGBTs), rated from 6 kV to 30 kV, for future grid conversion applications. Despite this early interest, there has been little work conducted on the optimal layout for the SiC IGBT, most early work seeking to overcome difficulties in fabricating the devices without a P+ substrate. In this paper, numerical TCAD simulations are used to examine the link between the carrier lifetime of SiC IGBTs and their short circuit capability. For the planar devices, simulations show that increasing carrier lifetime from 1 to 10 μs, has not only a profound effect reducing on-state losses, but also increases short circuit withstand time (SCWT) by 39%. Two retrograde p-well designs are also investigated, the optimal device for SCWT having a 100 nm channel region of 5×10¹⁶ cm^-3, with this increasing to a peak value of 2×10¹⁸ cm^-3, in a 700 nm region beneath the channel.

Abstract: In this work, the H3TRB performance of power modules with SiC MOSFET chips is investigated and compared to their silicon counterparts with similar electrical ratings. For this purpose, SiC MOSFETs and silicon IGBT chips are packaged in the same housing and with the same packaging technology and an H3TRB test is performed on both types of test devices. The results show that while both types exhibit an excellent H3TRB performance, the SiC MOSFETs had a significantly longer time to failure but also a wider failure distribution. Hence, the investigations presented in this paper confirm that properly designed SiC devices feature an equal or even better ruggedness against electro-chemical stress than standard silicon devics and are equally suitable for applications, which require operation in harsh environments.

Abstract: The 10 kV silicon carbide p-channel insulated gate bipolar transistors (IGBTs) with low forward voltage drop (V_F) have been fabricated and characterized successfully. The novel edge termination structure of Four-Region Multistep Field Limiting Rings (FRM-FLRs) and the optimum JFET region design proposed in our previous work is adopted to improve the blocking performance and the on-state characteristics. The fabricated device with a chip size of 6 mm × 6 mm and an active area of 0.16 cm² exhibits a high blocking voltage of -10 kV with a small leakage current below -200 nA. Meanwhile, a low forward voltage drop of -8 V at the collector current of -10 A with a gate bias of -20 V is obtained at room temperature, corresponding to a current density of 62.5 A/cm². Besides, a lower gate leakage current is measured less than 2 nA at the gate voltage of -30 V. Experimental results demonstrate that a better trade-off between the blocking voltage and the on-state characteristics is achieved for the fabricated device, which is desirable for the high power applications.

Abstract: In this study, to demonstrate the potential of the SiC-IGBT for high voltage application, we fabricated 13 kV class SiC-IGBT, and evaluated static characteristics and the ruggedness. The on-state forward voltage of 5.2 V at a collector current density of 100 A/cm² was obtained, and the breakdown voltage of 13.7 kV was achieved. Successful evaluation of SCSOA was obtained under the collector voltage of 4.6 kV, and utilizing the optimized layout with low saturation current, we realized the increase of the short circuit time. RBSOA turn-off was successfully achieved without any breakdown by latch up mode under the collector voltage of 4.0 kV and current density of 900 A/cm².

Abstract: In this paper, the structural cell design optimization of 15kV 4H-SiC p-channel IGBT is performed. The effects of the parameters of JFET region on the blocking voltage and the forward characteristics are analyzed by numerical simulations. The results indicate that the JFET width and JFET region concentration have an important effect on the performance of IGBTs. Based on the simulation structure in this paper, the optimum JFET width is 10μm, and the optimum JFET concentration is 7×10¹⁵cm⁻³. Meanwhile, they should be carefully designed to achieve the best trade-off between the blocking voltage and the forward voltage drop.

Abstract: 6.5-kV SiC IGBT with novel drift layer structure is developed to eliminate collector voltage steepening during turn-off and thus to suppress a ringing noise. The proposed IGBT has a depletion-controlled structure (DCS) of a two-step drift layer to suppress the increase of a depletion layer during the turn-off. We fabricated n-channel SiC IGBTs with DCS designed for a blocking voltage of 6.5 kV. Also, we applied our original backside-grinding-last (BG-last) process that enables low switching loss. The DCS device successfully reduced a riging of the gate voltage and had a turn-off loss of 17.6 mJ with 3.6-kV and 32-A switching operation. Although this value is larger than that of the conventional devices (8.8 mJ) due to a tail current, it is still quite low compared with the reported switching loss of SiC IGBTs with the proper switching curves, which is estimated to be 46.1 mJ with the same rated voltage and current.

Abstract: In this work we have studied the influence of design and process variations on electrical performance of 1.7 kV 4H-SiC Schottky diodes. Diodes with two variations in their active region design namely, stripe design and segment design, were fabricated in this study. Field Limiting Rings (FLRs) or Junction Termination Extension (JTE) were used as edge termination design to achieve a blocking voltage of 1.7 kV. In addition to these designs an extra processing step of nitrous oxide (N₂O) annealing was performed on some of the diodes. The study has shown that there is no extra beneficial effect of nitrous oxide annealing on device characteristics.