Papers by Keyword: Integrated Circuit

Abstract: In this study, we conducted in-situ measurements on a SiC JFET operational amplifier operating under gamma-ray irradiation. It shows that the radiation did not affect the output waveform or voltage gain, but shifted the output offset voltage. This shift may result mainly from holes generated by irradiation and trapped in the oxide layer, which modified the I-V characteristics of the level-shifting diodes. It can be compensated by applying bias voltage, and it may also be prevented by optimizing the diode structure and/or circuit topology.

Abstract: With its excellent thermal conductivity, high critical breakdown field strength, and high temperature tolerance, Silicon Carbide (SiC) is widely used in the fabrication of power devices. In recent years, many vertical high-voltage SiC PiN diodes with superior performance have been reported. However, since the cathode-anode voltage in these devices is vertically blocked in the semiconductor, the on-chip isolation between the devices is difficult to achieve. For this reason, the vertical power device is typically employed for high power densities in single-device packages or power modules. In contrast, effective isolation between lateral high-voltage devices can be achieved by using isolation structures, which enables monolithic integration with lateral PiN diodes, transistors, and resistors to achieve control, routing, and power density regulation in smart power-integrated circuits (ICs). This work describes the design and fabrication process of a novel SiC high-voltage lateral PiN (HVLPN) diode with the addition of a lateral isolation structure with a thickness of 10 μm to achieve sufficient isolation between breakdown voltages and devices, as well as a solution for the deep etching of the SiC over 10 μm with a thick enough Hard Mask (HDM), which is required for the actual fabrication process.

Abstract: This work compares design layouts and circuit simulations of the next two prototype NASA Glenn SiC JFET-R IC fabrication runs designated “IC Gen. 12” and “IC Gen. 13”. Even though both generations employ the same physical JFET gate length and chip size, SPICE simulations predict drastic improvements to IC capabilities and performance metrics for Gen. 13 over Gen. 12. The main factors behind simulated performance differences are thinner n-channel layer leading to reduced operating voltages and switch to stepper-based photolithography that enables roughly 4-fold layout area reductions for functionally identical circuit blocks.

Abstract: This paper presents results from metal contact processing experiments towards the implementation of durable 500 °C high-frequency 4H-SiC bipolar junction transistors (BJTs). Specifically, p-type ohmic contacts have been demonstrated on a 0.25 μm-thick p-type homoepitaxial layer of doping 8 × 10¹⁸ ± 4 × 10¹⁸ cm^-3. Finally, preliminary current-voltage characteristics of fabricated BJTs are presented.

Abstract: This paper describes a first attempt to build and operate a multi-chip prototype lander control and sensor signal digitization electronics circuit board comprised of ten NASA Glenn IC Generation 11 SiC JFET-R IC chips in 460 °C, 9.4 MPa harsh Venus surface conditions. The lander circuit ceased electrical operation prematurely at 107 °C as the Venus chamber heated up. Microscopic post-test inspections indicate that only one of the ten SiC chips on the board failed. Most of circuit-damaging cracks observed on the failed chip corresponded to micron-scale irregularly-shaped dielectric film hillock defects. The study of these defects suggests minor processing changes to eliminate this suspected root failure cause.

Abstract: All prior reports of long-term 500 °C operation of SiC JFET-R ICs have noted the existence of an initial “burn-in” period of changes in measured electrical characteristics for the first few hundred hours oven-testing. This work reports measurements of “burn-in parasitic MOSFET conduction” that can substantially impact the performance of some circuits during initial heat-up of JFET ICs, but then subsequently disappears after a few hours of operation at 500 °C. The behavior appears generally consistent with the known MOS phenomenon of bias-temperature driven redistribution of mobile ionic contamination. Approaches for further mitigating this initial burn-in conduction mechanism are discussed.

Abstract: High purity copper and copper alloy targets are the key supporting materials for the interconnection of integrated circuits in advanced processes. In this article, the chemical composition and microstructure of Cu-0.6wt%Mn alloy were characterized by means of Glow Discharge Mass Spectrometry, Inductive Coupled Plasma Emission Spectrometer, Optical Microscope and Scanning Electron Microscope. The results show that the total impurity content for Cu-0.69wt%Mn alloy is less than 1 ppm. The three key impurities contents of Ag and Fe and Si could meet the requirement of electronic materials for integrated circuits by use of high purity raw material and appropriate melting and casting methods. Mn content at different positions along the diameter direction fluctuates slightly between 0.66~0.72 wt%, and completely distributed uniformly in the Cu matrix without any trace of aggregation. Due to the influence of raw materials and casting technology, defects such as porosity and carbon inclusion are easy to appear in as-cast microstructure. Therefore, it is necessary to develop new casting mould and casting processing to improve the quality of ingots.

Abstract: Ultra-pure copper sputtering target is a key material widely used in large-scale integrated circuits with 90-28 nm feature size. The copper target for 300 mm integrated circuit requires a reliable diffusion bonding between the ultra-pure copper target and the copper alloy backplate. The bonding ratio and bonding strength of diffusion bonding should reach over 99% and 80 MPa respectively. In this paper, the ascendant structure of electron beam welding united diffusion bonding with high quality was designed. The ultra-pure copper target and the C18000 copper alloy backplate were machined to coordinating size, meanwhile the backplate underwent surface treatment of toothed/smooth, ion cleaning, magnetron sputtering coating, then the combination of target and the backplate was proceeded electron beam welding and diffusion bonding. Metallographic microscope, scanning electron microscope (SEM), mechanical tensile machine, C-scan flaw detector were used to analyze the bonding properties including interface microstructure, bonding strength and bonding ratio. The results show that the bonding ratio of copper target was above 99%, and the bonding strength was up to 80-160 MPa.

Abstract: Prolonged 500 °C to 700 °C electrical testing data from 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) are combined with post-testing microscopic studies in order to gain more comprehensive understanding of the durability limits of the present version of NASA Glenn's extreme temperature microelectronics technology. The results of this study support the hypothesis that T ≥ 500 °C durability-limiting IC failure initiates with thermal stress-related crack formation where dielectric passivation layers overcoat micron-scale vertical features including patterned metal traces.

Abstract: Silicon Carbide (SiC) is an attractive candidate for integrated circuits (ICs) in harsh environment applications due to its superior inherent electrical properties. Though current research is geared towards adapting existing silicon based digital logic technologies to 4H-SiC, the true merit of each technology in 4H-SiC has remained unclear. Creating logic technologies specifically for 4H-SiC, taking into account its electrical properties, is an area which remains unexplored. In this paper, we present a novel bipolar logic technology that is designed and optimized for 4H-SiC, and compare its performance with the prevalent bipolar technologies. The results show that the novel logic technology not only compares well with the conventional technologies in performance, but also features simpler design, smaller footprint, and a low transistor count.