Papers by Keyword: JFET

Abstract: In this study, we conducted in-situ measurements on a SiC JFET operational amplifier operating under gamma-ray irradiation. It shows that the radiation did not affect the output waveform or voltage gain, but shifted the output offset voltage. This shift may result mainly from holes generated by irradiation and trapped in the oxide layer, which modified the I-V characteristics of the level-shifting diodes. It can be compensated by applying bias voltage, and it may also be prevented by optimizing the diode structure and/or circuit topology.

Abstract: In this paper we study and compare two designs of a temperature sensor monolithically integrated to a vertical SiC JFET. One sensor utilizes the standard JFET P+ aluminum gate implantation scheme. The advantage of this sensor is that the integration with a JFET process flow can be achieved with no additional process steps or mask layers. The other sensor uses a combination P-body and a low energy P+ implantation scheme, typically seen in MOSFETs. Both sensors exploit the variation of resistance with temperature of Al doped SiC. Drift-Diffusion simulations of both designs are carried out at fixed temperatures, exhibiting an excellent ~53% relative reduction in sensor resistance from 300 to 450K. However, neither design shows linear behavior with temperature, beginning to saturate at 450K. Electrothermal simulations are also deployed to verify the sensor robustness as the sensor is locate relatively far from the JFET junction. Due to the high thermal conductivity of SiC, the sensor average temperature follows closely the junction temperature. Current crowding (or 2D effects) close to the contact edges is observed in both sensors. We also deploy a simple analytical model to calculate the resistance as a function of the temperature for both sensors. The model agrees with the drift-diffusion calculations, however due to the 2D nature of current flow, a maximum 19.6% relative error is obtained. In general, both sensors deployed similar relative sensitivity, however the P-body sensor resistance changes in a range of 10.6kΩ to 4.95kΩ compared to 700Ω to 330Ω for the P+ sensor.

Abstract: In the 4H-SiC device fabrication process, ion implantation of aluminium to form p-regions results in spreading (lateral straggling) from the mask design width by a few 100 nm. This has a significant impact on device performance, so device design must take lateral straggling into account. In this study, the impact of lateral straggling is estimated by applying a Gaussian distribution to one dimensional depth profiles obtained from Monte Carlo simulations. In our studies, this approach reduced the computation time by a factor of 300 compared to two-dimensional Monte Carlo simulations. The parameters describing the Gauss function are determined with the aid of fabricated JFET test structures. The pinch-off behaviour of JFET devices with vertical and horizontal channels was analysed in electrical TCAD simulations and calibrated to the characteristics of the fabricated devices. Ultimately, the electrical characteristics of simulations and measurements were found to be in good agreement.

Abstract: Investigation of the doped areas in 4H-SiC power devices has been done by non-destructive characterization methods. It consists of local surface potential measurements by Kelvin Probe Force Microscopy (KPFM) coupled with scanning electron microscopy (SEM) and µ-Raman spectroscopy. Near-field mappings of the devices’ surface have been realized, allowing us to discern the differently doped areas.

Abstract: This paper describes a first attempt to build and operate a multi-chip prototype lander control and sensor signal digitization electronics circuit board comprised of ten NASA Glenn IC Generation 11 SiC JFET-R IC chips in 460 °C, 9.4 MPa harsh Venus surface conditions. The lander circuit ceased electrical operation prematurely at 107 °C as the Venus chamber heated up. Microscopic post-test inspections indicate that only one of the ten SiC chips on the board failed. Most of circuit-damaging cracks observed on the failed chip corresponded to micron-scale irregularly-shaped dielectric film hillock defects. The study of these defects suggests minor processing changes to eliminate this suspected root failure cause.

Abstract: All prior reports of long-term 500 °C operation of SiC JFET-R ICs have noted the existence of an initial “burn-in” period of changes in measured electrical characteristics for the first few hundred hours oven-testing. This work reports measurements of “burn-in parasitic MOSFET conduction” that can substantially impact the performance of some circuits during initial heat-up of JFET ICs, but then subsequently disappears after a few hours of operation at 500 °C. The behavior appears generally consistent with the known MOS phenomenon of bias-temperature driven redistribution of mobile ionic contamination. Approaches for further mitigating this initial burn-in conduction mechanism are discussed.

Abstract: In this paper, 4H-SiC planar MOSFETs were designed and fabricated. By using TCAD tool, the trade-off between on-resistance and maximum gate oxide electric field was optimized. With optimized gate oxide growth process, the gate oxide’s critical electric field of 9.8 MV/cm and the effective barrier height of 2.57 eV between SiO₂ and 4H-SiC were obtained. The field effective mobility with different p-body doping was compared and studied. The MOS interface state density of 1.12E12 cm^-2eV^-1 at E_C - E_IT = 0.21 eV and channel mobility of 19.3 cm²/Vs at V_GS = 20 V were obtained. The fabricated MOSFET’s on-resistance of 6.4 mΩcm² was obtained with hexagonal cell structure which is very consistent with the simulation results.

Abstract: Silicon carbide junction field effect transistors (SiC JFETs) were irradiated with gamma-rays up to 9 MGy (H₂O). With increasing dose, apparent shift of drain current-gate voltage (I_D-V_G) curves to negative voltage side as observed for SiC metal oxide semiconductor (MOS) FETs did not take place. No significant difference is observed between drain and gate leakage currents of irradiated JFETs. This strongly indicates that defects as leakage paths were introduced into not bulk region but the interface between bulk and the passivation layer of SiO₂. While, the transfer characteristics including threshold voltage and transconductance were slightly changed compared with the pristine sample. After drain voltage (V_D) was abruptly applied to 6 V, I_D at V_G= 0 V increased slowly as a function of time. This indicates that variation of transfer characteristics is attributed to capture and emission process at defects generated in channel region.

Abstract: This paper presents results on developing high temperature capable SiC JFET based IC technology that can operate at temperatures up to 500 °C. All JFET devices are fully planar, formed by ion implantation, and the device design allows the use of semi-insulating or conductive SiC substrates. Basic analog and logic ICs were built in order to demonstrate the technology high temperature capability. All circuits used enhancement mode n-channel JFETs as active transistors, and depletion mode transistors as active loads. The logic circuits built included NOT, NAND, and NOR gates. The analog circuits built included a simple one-stage operational amplifier. JFETs and ICs were packaged in ceramic packages and tested at temperatures up to 500 °C.

Abstract: While NASA Glenn Research Center’s “Generation 10” 4H-SiC Junction Field Effect Transistor (JFET) integrated circuits (ICs) have uniquely demonstrated 500 °C electrical operation for durations of over a year, this experimental work has also revealed that physical cracking of chip dielectric passivation layers ultimately limits extreme-environment operating lifetime [1-3]. The prevention of such dielectric passivation cracks should therefore improve IC high temperature durability and yield, leading to more beneficial technology adoption into aerospace, automotive, and energy systems. This report describes Generation 10.2, 11.1, and 11.2 die tested under unbiased and unpackaged accelerated age testing at 500 °C, 600 °C, 720 °C, and 800 °C in air-atmosphere ovens for 100-and 200-hour duration. Additional samples were separately subjected to 10 thermal cycles between the same high temperatures (with 10-hour high-temperature soak each cycle) and 50 °C. It is shown that having two stoichiometric Si₃N₄ layers in the interconnect dielectric stack substantially decreases the amount of dielectric cracking observed following these oven tests.