Papers by Keyword: JFET

Abstract: A SiC-based high-performance Intelligent Power Modules (IPM) was developed. It is a System In Package (SIP) module that consist of a half-bridge with driver. In the developed SIP IPM, the internal half-bridge is made up of UnitedSiC 35mΩ/1200V Stack-Cascode switches (UF3SC120035Z) which have low on-resistance, low gate charge, simple gate drive of V_GS=0 or-5V to V_GS=12V, excellent integral body diode and very low switching losses. The module operates with control voltage of 12-15V for both the low and high side switches, and a logic level input that can be 3.3V, 5V or 12V. We believe that this module will enable extremely efficient switching up to 250-400kHz, depending on topology, offering several hundred kHz even in hard-switched applications.

Abstract: The prospects for beneficial application of integrated circuit (IC) capabilities in ambient environments above 450 °C have been significantly improved by recent long-term demonstrations of SiC chips and packaging by NASA Glenn Research Center. This invited paper reviews and updates development of durable SiC IC technology aspects relevant to engineering infusion into beneficial applications, including the first long-duration low-mass Venus lander missions

Abstract: Stress tests were conducted for the cascode switch using the SiC buried gate static induction transistor (SiC-BGSIT). The stress of the reverse overshoot voltage was periodically applied to the pn junction between the gate terminal and source one in the BGSIT in the cascode with pulses of 40kHz for 202 hours. This simulates the stress which can be occurred in the channel region of the BGSIT during the turn-off and turn-on operation with a parasitic inductance in the interconnection of the cascode package. The result of the stress tests has revealed that there is no significant difference between the electrical characteristics of the BGSIT cascode sample before the stress and those after the stress. Thus, the BGSIT cascode can guarantee high reliability against the stress. The result from the drain current DLTS suggests that no deferent kind of defect is created in the channel region of the BGSIT by the stress.

Abstract: High temperatures and other harsh environments are domains of predilection for Junction FETs, particularly when wide band-gap semiconductors such as SiC or GaN are used. The present work describes the new compact model of double gate (DG) JFETs which is compared to TCAD simulations of SiC and GaN JFETs over a wide temperature range up to 500oC. The compact model is shown to be predictive of device behavior, for static (current-voltage) as well as dynamic (capacitance-voltage) behavior of long-channel DG JFETs.

Abstract: Silicon carbide (SiC) n-and p-channel junction field effect transistors (JFETs) with vertical channels were fabricated by direct ion implantation into a high-purity semi-insulating 4H-SiC substrate in order to further develop the path towards complementary JFET integrated circuits for applications in harsh environments. Compared with the conventional structure (lateral channel), the proposed structure is suitable for integration and inherently has a high transconductance owing to the double-gate configuration. The threshold voltage (V_th) can be controlled by mask design, while V_th in the conventional structure is solely determined by the ion implantation conditions. We demonstrate the transistor operation of the vertical-channel n-and p-channel JFETs fully fabricated by ion implantation.

Abstract: Operational testing of prototopye 4H-SiC JFET ICs across an unrivaled ambient temperature span in excess of 1000 °C, from-190 °C to +812 °C, has been demonstrated without any change/adjustment of input signal levels or power supply voltages. This unique ability is expected to simplify infusion of this IC technology into a broader range of beneficial applications.

Abstract: This report describes more than 5000 hours of successful 500 °C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 °C. After 100 hours of 500 °C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 °C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 °C in comparison to what is observed for Earth-atmosphere oven testing at 500 °C.

Abstract: Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC’s with two levels of metal interconnect capable of prolonged operation at 500 °C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 °C. A 3-stage oscillator functioned for over 3000 hours at 500 °C in air ambient. Improved reproducibility remains to be accomplished.

Abstract: In switching applications with half-bridge like configurations the load current is commutated to the so-called reverse or body-diode of a switching device once each switching cycle. The bipolar charge generated in the switch in principle leads to a reverse recovery current and to additional losses. Though it is well known, that in silicon carbide these reverse recovery losses are very low compared to e.g. silicon devices, it turns out that depending on device structure and switching conditions the reverse recovery charge for the JFET may become larger than can be explainable by the stored bipolar charge. In this paper therefore we focus on a simulation study comparing the body-diode operation of common lateral channel silicon carbide JFET and MOSFET devices in a so-called double pulse measurement. It is shown, that the MOSFET body-diode operation still remains uncritical under very fast switching conditions, while the JFET body-diode exhibits a pronounced recovery current peak originating from a partial channel turn-on, and thus higher losses.

Abstract: This work reports a theoretical and experimental study of 4H-SiC JFET threshold voltage as a function of substrate body bias, device position on the wafer, and temperature from 25 °C (298K) to 500 °C (773K). Based on these results, an alternative approach to SPICE circuit simulation of body effect for SiC JFETs is proposed.