Papers by Keyword: Junction Termination Extension (JTE)

Abstract: A charge-imbalanced P-pillar distribution termination (D3) is proposed for 1500 V-class 4H-SiC superjunction (SJ) devices. By combining a junction termination extension (JTE)-based termination with gradually widened P-pillar spacing, the design effectively suppresses edge electric field crowding and enhances device reliability. TCAD simulations show that D3 achieves comparable blocking capability while exhibiting significantly improved robustness against charge imbalance, oxide charge density, and JTE dose deviations, demonstrating superior process margin and reliability. With relaxed process sensitivity and an efficient structure, D3 presents a promising approach for high-voltage 4H-SiC SJ device fabrication.

Abstract: This work reports enhanced high-voltage blocking capability and an enlarged process window for junction termination extension (JTE) in SiC power devices using a hybrid random and channeling implantation for p-type doping (Al), compared with conventional random-only implantation. A three-step hybrid implantation process has been developed to replace a nine-step random implantation, achieving a similar doping profile and equivalent breakdown voltage in the JTE while significantly increasing fabrication productivity and reducing cost. Moreover, TCAD studies reveal that when using the same number of steps and ion energies as the conventional random implantation method, the JTE realized by the channeling-incorporated hybrid approach enables an increased breakdown voltage and a widened dose window in SiC devices. This is attributed to a deeper Al distribution with a lower average concentration, which effectively alleviates electric field crowding.

Abstract: This paper discusses SiC JTE design tradeoffs required to maximize device performance while minimizing consumed die area, fabrication cost and maintaining good reliability. Modeling and experimental results are provided.

Abstract: Impact ionization coefficients are important material properties that determine the breakdown voltage and safe operating area of power devices. This paper presents an anisotropy breakdown model with modified parameters that reproduces well experimental results for both peak breakdown voltages and sharp drops in breakdown voltage at high junction–termination–extension (JTE) acceptor concentrations. Using a newly developed simulation model, we optimized the edge termination and current-spreading layers (CSLs) and obtained a low specific on-resistance (R_ONA) of 11.6 mΩcm² for a breakdown voltage (BV_DSS) of approximately 4 kV and a high-avalanche-withstanding energy robustness of 4.6 Jcm^-2.

Abstract: Ion implantation in silicon carbide (SiC) induces defects during the process. Implantation free processing can eliminate these problems. The junction termination extension (JTE) can also be formed without ion implantation in SiC bipolar junction transistor (BJT) using a well-controlled etching into the epitaxial base layer. The fixed charges at the SiC/SiO₂ interface modify the effective dose of the JTEs, leakage current, and breakdown voltage. In this paper the influence of fixed charges (positive and negative) and also interface trap density at the SiC/SiO₂ interface on the breakdown voltage in 4.5 kV 4H-SiC non-ion implanted BJT have been simulated. SiO₂ as a surface passivation layer including interface traps and fixed charges has been considered in the analysis. Simulation result shows that the fixed charges influence the breakdown voltage significantly more than the interface traps. It also shows that the positive fixed charges reduce the breakdown voltage more than the negative fixed charges. The combination of interface traps and fixed charges must be considered when optimizing the breakdown voltage.

Abstract: In this study, a new robust double-ring junction-termination-extension (DR-JTE) for high-voltage pn-diodes is presented and analyzed using numerical simulations. As figured out, the DR-JTE reduces the electrical field at both, the edge of the single-JTE region and the MESA-transition, respectively. Thereby, due to the reduction of the electrical field, the maximum breakdown voltage is increased to 91.5% of the theoretical, parallel-plane breakdown voltage of 6.5kVand the maximum acceptable deviation of the optimum implantations dose is twice than that of the single-JTE structure. Furthermore, due to the internal ring, the MESA-transition is shielded from the electrical field and therefore the breakdown voltage is much less affected by the angle of the MESA.

Abstract: The influences of positive fixed oxide charges and donor-like interface traps on breakdown voltages of SiC devices with FGR and JTE terminations were studied. The breakdown voltages of devices with both FGR and JTE terminations were found to degrade when the level of fixed oxide charges overs 1×10¹² cm^-2 due to enhancement of junction curvature by fixed oxide charges. The introduction of donor-like interface traps at the interface shows similar behaviors as fixed positive charges, suggested that both fixed oxide charges and interface traps should be taken into account when one optimizes device designs and processes.

Abstract: The static performance of different active and termination area designs for SiC-based Schottky diodes, suitable for 3.3kV applications, were investigated by means of extensive numerical simulations. We found quantitatively that the high electric field of SiC close to avalanche-breakdown is shielded most effectively from the Schottky interface by a trench-based design. Moreover, we conclude that the edge termination design with junction termination extension and four implanted p⁺ guard rings is most robust against oxide interfacial charge.

Abstract: Ultrahigh-voltage SiC PiN diodes with an original junction termination extension (JTE) structure and improved forward characteristics are presented. A space-modulated JTE (SM-JTE) structure was designed by device simulation, and a high breakdown voltage of 26.9 kV was achieved by using a 270 μm-thick epilayer and 1050 μm-long JTE. In addition, lifetime enhancement process via thermal oxidation was performed to improve the forward characteristics. The on-resistance of the SiC PiN diodes was remarkably reduced by lifetime enhancement process. The temperature dependence of the on-resistance was also discussed.

Abstract: This paper presents and compares different avalanche breakdown voltage estimation methods in 4H-SiC (silicon carbide) using finite element simulation results on Schottky diode. 4H-SiC avalanche breakdown voltage and depletion width estimated with Baligas equations have shown to be higher than other estimation techniques and simulation results, especially for voltages higher than 5kV. This paper discusses the impact of choosing different junction termination extension (JTE) structures on two-dimensional junction curvature effects and electric field crowding for Schottky diodes Space-Modulated JTE (SMJTE) structure with optimum JTE dose and dimension could achieve up to 90% of the parallel plane breakdown voltage. For ultra high voltage devices (>15 kV) the SMJTE has significant improvement in terms of breakdown voltage. It also has a wider optimum JTE dose window. For 1 kV device there is not a significant difference in breakdown voltage between JTE and SMJTE structures.