Papers by Keyword: Low Power

Abstract: SRAM (Static Random Access Memory) is an essential component of memory devices such as laptops, phones, etc., which act as a semiconductor memory. The “Carbon Nanotube Field Effect Transistor (CNTFET)” is silicon associated high-stability, low-power device with excellent performance. CNTFET has been verified to be very advantageous for Very large-scale integration circuit designs in the nanoscale range because of its remarkable properties of metal oxide semiconductor field effect transistor (MOSFET). The material was brought to light because of its genuinely incredible electrochemical performance. Carbon nanotubes have unique properties such as high charge carrier mobility, high voltage, small footprint, exceptionally short and high control over pulse duration, and large current densities. In traditional MOSFET, bulk silicon is used, which has high leakage current and high field-effect; thus, CNTFET has been used as an alternative in recent years. When compared to the 10T CNTFET SRAM Bit cell is designed using HSPICE Tool in 22nm technology. Long-term stability and significant process variable changes are significant challenges with nanoscale SRAM cells.

Abstract: Dissimilar aluminum alloys, AA2024-0 and AA7075-T6 were laser welded on both sides in a T-joint configuration using a low power fiber laser. The effect of welding speed (9, 12, 15, 18 and 21 mm/s) on weldability was evaluated at laser power of 270W with argon gas as the shielding gas. The sample welding angle was fixed at 45^° with an interval of 180 seconds between each welding pass. Macrograph observations revealed that full penetration with pore free weld of these dissimilar joint was obtained at the laser parameters of 270 W and 9 mm/s, suggesting that lower welding speed is preferred during low power laser welding.

Abstract: This work proposes a technique for optimizing data placement of application-wide reused data so that it resides in scratchpad memory of processing elements in multiprocessor system on chips. The proposed technique identifies data elements with fine granularity that can profitably be placed in the scratchpad memories to maximize performance and energy gains. We present a heuristic approach that efficiently exploits the scratchpad memories using memory access footprint. Our experimental results indicate that our approach is able to reduce energy consumption by 30% over cache based memory subsystems.

Abstract: Embedded systems demand to take high performance while executing on batteries. In such environment, the systems must be optimized with available technique to reduce energy consumption while not sacrificing performance. Especially, in mobile devices, power consumption is an important design constraint. Switching activity accounts for over 90% of total power consumption in a digital circuit. In this paper, we describe an approach to design instruction format for low power instruction fetch. The proposed method reduces switching activity of the instruction fetch logic by using a heuristic that minimizes switching between adjacent instructions. To do this, the proposed approach encodes opcodes so that frequently executed instruction pairs have smaller bit changes.

Abstract: The new digital control loop of the low-dropout regulator (LDO) is presented. It is composed of coarse tracking circuit and fine tracking circuit, and no external output capacitor is required to stabilize the control loop. The proposed method makes the quiescent current lower than conventional analog LDOs. The operational amplifier of the conventional LDO fails to operate at 0.7V, and the developed digital LDO in 0.18um CMOS achieved the 0.7V input voltage and 0.5V output voltage with 99.99% current efficiency and 2.6-μA quiescent current at 20mA load current. Therefore, the proposed DLDO is suitable for low power applications.

Abstract: In order to reduce the power consumption of handset GNSS receivers, we present a novel algorithm that tracks signals at fixed positions of the navigation message in an intermittent mode. The tracking channels only run during the beginning part of the message frame. In the rest they remain in idle state, to reduce power consumption of the channel. The beginning position of each message frame can be estimated accurately, and the beginning messages are constant or can be estimated, thus the coherent integration time can exceed one navigation bit, which can improve the Doppler frequency estimated accuracy. At the fixed position of the frame, the tracking channel only tracks the pseudo-code phase, and does not track the carrier frequency and phase. This algorithm can keep stable tracking for weak signals with 28 dBHz carrier-to-noise ratio (C/N0), while using only 2% of the power required by the computation associated with the traditional tracking.

Abstract: With the development of digital very large scale integrated circuits (VLSI), how to reduce the power dissipation and improve the operation speed are two aspects among the most concerned fields. Based on sense amplifier technology and bulk-controlled technique, this paper proposes a bulk-controlled sense-amplifier D flip-flop (BCSADFF). Firstly, this flip-flop can change the threshold voltage of the NMOS by inputting control signals from the substrate so as to control the operating current. Secondly, the traditional RS flip-flop composed of two NAND gates is improved to a couple of inverters based on pseudo-PMOS dynamic technology. Therefore, the proposed BCSADFF can both effectively reduce the power dissipation and improve the circuit speed. Thirdly, the designed BCSADFF can work normally with ultra-dynamic voltage scaling from 1.8 V to 0.6V for SMIC 0.18-um standard CMOS process. Lastly, the Hspice simulation result shows that, compared with the traditional sense-amplifier D flip-flop (SADFF), the power dissipation of the BCSADFF is significantly reduced under the same operating conditions. When the power supply voltage is 0.9V, the power dissipation and delay of the SADFF is 6.54uW and 0.386ns while that of the proposed BCSADFF is 2.09uW and 0.237ns.

Abstract: An ideal capacitor will not dissipate any power, but a real capacitor will have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM with frequencies (2.9GHz, 3.3GHz, 3.6GHz, 3.8GHz and 4.0GHz) supported by i7 processor.By using different capacitance there comes is reduction in I/O Power and Total power but not in other Powers like Clock, and Leakage (almost negligible). When capacitance goes from 30pF to 5pF, there is a saving of 28.12% occur in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog.

Abstract: For the deficiencies of the existing complex circuit designs, a novel transistor-level three-input AND/XOR logic complex gate with simple and symmetry structure is proposed. HPSICE simulation results show that the proposed circuit has correct operation. Further, in 55nm process CMOS technology, compared with the conventional cell-based cascaded AND/XOR circuit at different operation frequencies, the proposed circuit has a significant improvement at delay, power consumption and power delay product (PDP).

Abstract: An analysis of the output impedance of the reference buffer for pipelined ADC is presented is this paper. To achieve high performance of the reference buffer, damping network has added in. The output impedance of buffer amplifier is made equal to the resistance of the damping network. As a result, the effective impedance is made independent of frequency. Spectre simulation with 14-bit 250MSPS pipelined ADC loads, the results show the settling time can be achieved 1.2 ns with 0.0023% precision, and the noise floor per bin is-114dB with the power consumption is 42.3mW. The reference buffer can meet the requirement of 14-bit up to 800MSPS pipelined ADC.