Papers by Keyword: MOS

Abstract: In this work, a comparison of standard bulk 4H-SiC epi wafers and Soitec's SmartSiC™ wafers as well as the influence of RTA processing was conducted. For this, MOS capacitors were processed using thermal gate oxide paired with a polycrystalline gate electrode. Subsequent High temperature steps were avoided until an RTA process was performed on some of these wafers. To investigate the oxide quality on all wafer and process splits, CV-, time-zero dielectric breakdown and constant-current stress time-dependent dielectric breakdown measurements were carried out. For the examination of bulk wafers and SmartSiC™, no relevant differences in terms of yield, oxide quality, interface state density and reliability were found. In contrast, RTA processes seem to create a shift in flat band voltage and also lead to a reduction in oxide lifetime. The V_FB shift could partially, but not completely, be explained by addition activation of dopants in the polysilicon electrode. The influence on the oxide reliability, however, is still unclear.

Abstract: This paper presents a macro-and nanoscale electrical investigation of Schottky and metal-oxide junctions with hetero-epitaxial 3C-SiC layers grown on Si. Statistical current-density-voltage (J-V) characterization of Pt/3C-SiC Schottky diodes showed an increase of the reverse leakage current with increasing the devices diameters. Furthermore, C-V and J-V analyses of SiO₂/3C-SiC capacitors revealed non-idealities of the thermal oxide, such as a high trapped positive charge (3×10¹² cm⁻²) and a reduced breakdown field (E_BD=6.5 MV/cm) compared to ideal SiO₂. Nanoscale electrical characterizations by conductive atomic force microscopy (CAFM) and scanning capacitance microscopy (SCM) allowed to shed light on the origin of non-ideal behavior of Schottky and thermal oxide junctions, by correlating the morphological features associated to 3C-SiC crystalline defects with local current transport and carrier density.

Abstract: In this paper, SiC MOS capacitors were fabricated and annealed in Ar/O₂ = 9:1 ambient with different temperature, and the annealing effects on the reliability and performance of SiC MOS capacitance were investigated. We found that annealing in Ar/O₂ ambient is capable to improve the reliability of gate oxide. When annealing in higher temperature, defects near SiO₂/SiC interface are reduced, but the gate reliability deteriorated. It is difficult to obtain the best performance and reliability under the same conditions. There is a trade-off between D_it and reliability to adjust the annealing conditions.

Abstract: In this work, the influence of pre-deposition interfacial oxidation or post-deposition interface nitridation on the performance of 4H-SiC MOS capacitors was investigated. The gate oxide was deposited by LPCVD using TEOS as a precursor. Interface breakdown strength was derived from leakage current and Time-Zero Dielectric Breakdown characteristics whereas interface quality was assessed by the determination of interface state density from the comparison of quasi-static and high frequency capacitance-voltage characteristics using high-low method. In the experimental results, it is demonstrated that the gate oxide deposited by LPCVD using TEOS which is post-deposition annealed in nitric oxide ambient is advantageous for trench-gate MOSFET due to its effectiveness for improving the interface quality and oxide reliability, whereas pre-deposition interfacial oxidation is deleterious to interface state density and breakdown strength.

Abstract: We used the POCl₃ gate technique for the fabrication of 4H-SiC vertical MOSFETs, and examined its effect on the V_TH-R_ON tradeoff and the compatibility with device fabrication. The gate oxide film was formed by thermal dry O₂ oxidation followed by POCl₃ or NO annealing. The POCl₃ process reduced R_ON by about 30% compared with the NO process for the ones having V_TH of 1.1 V, being attributed to the channel mobility enhancement. Moreover, the improvement was more effective for higher V_TH designs. The conventional thermal treatment after the gate process considerably spoiled the channel mobility improvement brought by the POCl₃ annealing and strengthened negative charge trapping in the gate oxide. The presumed extra-formed defects also affected the E_OX dependence of t_BD on the TDDB tests, being expected to shorten the gate oxide lifetime under practical device operation stress. Successful insertion of the POCl₃ process into production lines depends upon careful low-temperature post processing.

Abstract: In this paper, the electrical properties of a thermal oxide (SiO₂) grown onto 3C-SiC layers on silicon were investigated, by monitoring the behavior of MOS capacitors. In particular, the growth rate of thermal SiO₂ was dependent on the different surface roughness condition. However, independent of the roughness a high density of positive charge was detected. The sample having the smooth surface (subjected to CMP) showed a notably improved dielectric breakdown (BD) field. However, the best BD on macroscopic MOS capacitors was still far from the ideal behavior. Additional insights could be gained employing a nanoscale characterization that revealed the detrimental role of persisting extended defects in the semiconductor. In the semiconductor region far from extended defects the nanoscale BD kinetics was nearly ideal.

Abstract: A quantitative analysis method was proposed for near-interface oxide traps (NITs) at the SiC-MOS interface. Based on the tunneling capture model for electrons to the traps, characteristic parameters of NITs were clearly extracted from the pulse width dependence of the constant-capacitance deep-level transient spectroscopy (CC-DLTS) signal amplitude measured under isothermal conditions. To exclude capture processes other than direct tunneling, the pulse voltage was set to the flat-band voltage. The validity of the assumed model, in which the majority of the traps are localized at the interface and not distributed through the whole depth of the oxide, was demonstrated through comparison of the experimental results for two samples with different oxide thickness. The density of NITs at the MOS interface fabricated on 4H-SiC oxidized in a N₂O atmosphere slowly decreases with the energy depth. The capture cross-section at the interface has no energy dependence, and has a value of 10^-19 cm².

Abstract: Surface morphology and electrical properties of silicon dioxide (SiO₂) on 4H-SiC substrates formed by metal-enhanced oxidation (MEO) using barium (Ba) atoms were systematically investigated. It was found that severe surface roughening caused by Ba-MEO can be suppressed by using SiO₂ capping prior to MEO. The Ba atoms at the SiO₂/SiC interface were found to diffuse to the oxide surface through the deposited SiO₂ capping layer, and then the Ba density reduced to ~10¹⁴ cm^-2 before stable MEO. The resulting SiO₂/SiC interface showed the reduced interface state density but the insulating property of the oxides was significantly degraded.

Abstract: Normally-on MOSFETs were fabricated on 3C-SiC epilayers using high temperature (1300 °C) wet oxidation process. XPS analysis found little carbon at the MOS interface yet the channel mobility (60 cm²/V.s) is considerably low. Si suboxides (SiO_x, x<2) exist at the wet oxidised 3C-SiC/SiO₂ interface, which may act as interface traps and degrade the conduction performance.

Abstract: In this paper, an analytical model for evaluation of tunneling current density of ultra-thin Metal Oxide Semiconductor (MOS) devices is presented. Results have been obtained for a wide variation of oxide thickness and biasing condition having doping concentration of 1 x 10¹⁷ cm^-3. The investigation for the tunneling current density is limited to low temperatures, so that any thermal involvement to current flow can be neglected. The self-consistent oxide tunneling model has been used for device simulation, which is simple to implement and assist in the study of deep sub-micron MOS gate current effects, therefore correctly calculate the terminal current. Tunnel resistivity is also evaluated utilizing this tunneling current density model. Theoretical predictions are compared with the results obtained by the 2-D numerical device simulator ATLAS, good agreements between the two are observed.