Papers by Keyword: MOS

Abstract: Silicon carbide based devices have the potential to surpass silicon technology in high power, high frequency and high temperature applications. 4H-SiC MOS transistors currently suffer from a low channel mobility due to a high density of traps near the oxide/SiC interface. In this work, oxides have been grown on the Si face of 4H-SiC using oxygen flow rates ranging from 2.5 l/min to 0.05 l/min. Capacitance-voltage measurements on MOS capacitors revealed approximately a fourfold reduction in the interface trap density and a 25% increase in oxide thickness by reducing the flow rate from 2.5 l/min to 0.05 l/min.

Abstract: A 4kbps vocoder based on MELP is presented in this paper. It uses the parameter encoding and mixed excitation technology to ensure the quality of speech. Through adopting the scalar quantization of Line Spectrum Frequency (LSF), the algorithm reduces the storage and computational complexity. Meanwhile, 4kbps vocoder adds a new frame type-transition frame. The classifier can reduce the U/V decision errors and avoid excessive switching between voiced frame and unvoiced frame. A modified bit allocation table is introduced and the PESQ-MOS and coding time test shows that the synthetic speech quality has been improved and reached the quality of communication.

Abstract: The effect of annealing temperature on the properties of c-Si wafer/SiO_x interface (x = 1.15 and 1.3) is studied by Transmission Electron Microscopy and Capacitance/Conductance-Voltage measurements. Furnace annealing for 60 min at 700 and 1000 °C is used to grow amorphous or crystalline Si nanoparticles. The high temperature process leads to an epitaxial overgrowth of the Si wafer and an increase of the interface roughness, 3-4 monolayers at 700 °C and 4-5 monolayers at 1000 °C. The increased surface roughness is in correlation with the higher density of electrically active interface states.

Abstract: The Integrated Evaluation Platform for SiC wafers and epitaxial films is established and provide TDDB reliability data such as Q_bd. Accumulated numerous Q_bd data derived from the platform shows three discrete universal distributions (D1>D2>D3) mainly affected by step bunching. On the fairly flat surface, locally spreading step-bunching area formation is caused by the scratches on the CMP surface. The step-bunching area contains large number of step-bunching lines, which correspond to trapezoid-shape defects, stretching in a low along the scratches. Only the downstream bases of the trapezoid-shape defects degrade the Q_bd into D2 from D1 on the flat surface without step bunching.

Abstract: La_xHf_yO nanolaminated thin film deposited using atomic layer deposition process has been studied as a high-K gate dielectric in 4H-SiC MOS capacitors. The electrical and nano-laminated film characteristics were studied with increasing post deposition annealing (PDA) in N₂O ambient. The result shows that high quality La_xHf_yO nano-laminated thin films with good interface and bulk qualities are fabricated using high PDA temperature.

Abstract: In this work, we have developed a novel gate stack to enhance the mobility of Si face (0001) 4H-SiC lateral MOSFETs while maintaining a high threshold voltage. The gate dielectric consists a thin lanthanum silicate layer at SiC/dielectric interface and SiO₂ deposited by atomic layer deposition. MOSFETs using this interface engineering technique show a peak field effect mobility of 133.5 cm²/Vs while maintaining a positive threshold voltage of above 3V. The interface state density measured on MOS capacitor with lanthanum silicate interfacial layers is reduced compared to the capacitors without the silicate. It is shown that the presence of the lanthanum at the interface reduces the formation of a lower quality SiO_x interfacial layer typically formed at the SiC surface during typical high temperature anneals. This better quality interfacial layer produces a sharp SiC/dielectric interface, which is confirmed by cross section Z-contrast STEM images.

Abstract: A 1 cm x 1 cm 4H-SiC N-IGBT exhibited a blocking voltage of 20.7 kV with a leakage current of 140 μA, which represents the highest blocking voltage reported from a semiconductor power switching device to this date. The device used a 160 μm thick drift layer and a 1 μm thick Field-Stop buffer layer, and showed a V_F of 6.4 V at an I_C of 20 A, and a differential R_on,sp of 28 mΩ-cm². Switching measurements with a supply voltage of 8 kV were performed, and a turn-off time of 1.1 μs and turn-off losses of 10.9 mJ were measured at 25°C, for a 8.4 mm x 8.4 mm device with 140 μm drift layer and 2 μm F-S buffer layer. The turn-off losses were reduced by approximately 50% by using a 5 μm F-S buffer layer. A 55 kW, 1.7 kV to 7 kV boost converter operating at 5 kHz was demonstrated using the 4H-SiC N-IGBT, and an efficiency value of 97.8% was reported.

Abstract: TDDB for n-type 4H-SiC MOS capacitors depleted by DC bias (named as depletion-mode TDDB) has been investigated. The lifetime distribution can apparently be classified into two groups: shorter and longer t_BD. Breakdown for the shorter t_BD occurs at a point close to a threading dislocation. In contrast, the capacitors possessing longer t_BD include no dislocation. An increase in the stress temperature and/or E_OX leads to a decrease in t_BD, indicating that the breakdown is caused by gate-oxide degradation. On the other hand, the t_BD distributions acquired by accumulation-mode TDDB are relatively even, and the breakdown point is independent of dislocations. We presume that holes excited in the SiC layer by hot electrons play an important role at a threading dislocation for depletion-mode TDDB.

Abstract: Using Deep Level Transient Spectroscopy (DLTS) on n-type MOS capacitors we find that thermal oxidation of 4H-SiC produces deep traps at or near the SiO₂/SiC interface with two well defined DLTS peaks. The traps are located ~ 0.85 V and ~ 1.0 eV below the SiC conduction band edge and are present in wet and dry oxides as well as oxides produced by sodium enhanced oxidation and oxides grown in N₂O. The deep traps are located at the SiO/SiC interface after oxidation at 1150°C but do extend further into the SiC epilayer after oxidation at 1240°C. We identify these traps as ON1 and ON2 which been observed in epitaxial layers after oxidation at very high temperatures (1200-1500°C) [.

Abstract: Constant-capacitance deep-level transient spectroscopy was carried out to characterize in detail interface states close to the conduction band edge in SiO₂/SiC structures. The measured results are summarized as follows: (1) The capture of electrons by the interface states proceeds logarithmically with time. (2) The emission of electrons accelerates slightly with increasing density of captured electrons. The oxide trap model explains the logarithmic change in capture with time but not the phenomenon of accelerated emissions. This prompted us to formulate a new model that replicates the logarithmic capture process with time. In this model, we postulated the electron density at the interface decreases exponentially as the trapped electron density increases owing to the interaction between the trapped electrons and the free electrons. In this case, the capture process is almost the same as with the oxide trap model except for the definition of parameters. Further, we do not need to take into account the delay of the emission process caused by tunneling. The phenomenon of accelerated emissions may be explained by interactions among captured electrons in this model.