Papers by Keyword: MOS

Abstract: In this paper different characteristic parameters using high-k dielectric materials in Metal Oxide Semiconductor (MOS) device have been compared from the theoretical and simulated Capacitance-Voltage (C-V) graphs. The simulation has been done using ATLAS device simulator. The agreement of the specified values while deriving and simulating and that extracted is excellent. Further, the extracted parameters for high-k dielectric materials show an inferior interfacial quality.

Abstract: In this work, anomalous discontinuities observed in Capacitance-Voltage (C-V) characteristics on non-nitridated n-4H-SiC/SiO₂ capacitors at low temperature are addressed. The appearance of abrupt capacitance minima, always at the same gate voltages (4V and 8V) and independent on probe frequency, led us to consider a resonant electron tunneling process from neutral donor states present at the SiC/SiO₂ interface into two well defined energy levels in the oxide layer. Results of numerical simulations based on this model describe quantitatively the experimentally observed discontinuities at 4V and 8V and provide strong evidence for the presence resonant tunneling.

Abstract: We investigate the strong passivation of shallow interface traps located near the SiC conduction band after enhanced oxidation of Si-face 4H-SiC in the presence of sodium. We find that removing the sodium ions present at the SiO2/SiC interface since oxidation by way of bias stress or annealing does not lead to a significant increase in the density of interface traps. The presence of sodium ions at the SiO2/SiC interface is therefore not responsible for the passivation of such interface traps in oxides formed by sodium enhanced oxidation.

Abstract: In this paper, we report on a novel direct wafer bonding technique; Si (111) wafers to polycrystalline silicon carbide carrier wafers. The purpose of this work is to provide a platform for 3C-SiC epitaxial growth above the wafer bonded Si (111) wafers. We have demonstrated reduced wafer bow, confirmed by optical microscopy together with a digital camera. 3C-SiC epitaxial layers have been grown by conventional chemical vapor deposition techniques above Si/SiC structures. All of these 3C-SiC epitaxial layers are highly crystalline in nature. In the future, the realization of thick, bow-free 3C-SiC layers suitable for power device fabrication is achievable.

Abstract: Effects of combination of NO and POCl₃ annealing on electrical properties and their stability of 4H-SiC MOS capacitors and MOSFETs were investigated. Channel mobility of MOSFETs processed with both NO and POCl₃ annealing did not exceed that of POCl₃ annealed MOSFETs. As for the stability of flat-band voltage and threshold voltage using a constant field stress test, the combined annealed sample indicated very stable characteristics compared with single annealed devices with NO or POCl₃. The reason for obtaining stable electrical properties is discussed based on nitridation and phosphorization effects at the interface.

Abstract: 4H-SiC MOSFETs were characterized using charge pumping (CP) technique to monitor interface state density (D_it) not only in the upper half of the bandgap (E_g) but also in the lower half of E_g. Comparison between POCl₃- and NO-annealed MOSFETs was made using CP technique to reveal the different interface properties. The CP measurements of MOSFETs revealed that POCl₃ annealing can reduce D_it near E_c, whereas it increases donor-like D_it in the lower half of E_g.

Abstract: Metal-oxide-semiconductor (MOS) capacitors with phosphorus localized near the SiO₂/SiC interface were fabricated on 4H-SiC by direct POCl₃ treatment followed by SiO₂ deposition. Post-deposition annealing (PDA) temperature affected MOS device properties and phosphorus distribution in the oxide. The sample with PDA at 800 °C showed narrow phosphorus-doped oxide region, resulting in low interface state density near the conduction band edge and small flatband voltage shift after FN injection. The interfacial localization of phosphorus improved both interface properties and reliability of 4H-SiC MOS devices.

Abstract: In this paper, we characterized MOS devices fabricated on 4H-SiC (0-33-8) face. The interface state density of SiO₂/4H-SiC(0-33-8) was significantly low compared to that of SiO₂/4H-SiC(0001). The field-effect channel mobility obtained from lateral MOSFET (LMOSFET) was 80 cm²/Vs, in spite of a high p-well concentration of 5x10¹⁷ cm^-3 (implantation). The double implanted MOSFET (DMOSFET) fabricated on 4H-SiC(0-33-8) showed a specific on-resistance of 4.0 mΩcm² with a blocking voltage of 890 V.

Abstract: Constant-capacitance deep-level-transient spectroscopy (CCDLTS) characterization of traps (or states) in SiO₂/SiC interfaces on the C-face was carried out to clarify the cause of low-channel mobility of SiC MOSFETs. CCDLTS measurements showed that the interface-state density (D_it) near the conduction band of SiO₂/SiC interfaces fabricated using N₂O oxidation was much higher than that of SiO₂/SiC interfaces fabricated using wet oxidation. The high density of interface states near the conduction band is likely to be the main cause of the low mobility of MOSFETs fabricated using N₂O oxidation.

Abstract: This study focuses on the characterization of silicon dioxide (SiO₂) layers, either thermally grown or deposited on trenched 100 mm 4H-silicon carbide (SiC) wafers. We evaluate the electrical properties of silicon dioxide as a gate oxide (GOX) for 3D metal oxide semiconductor (MOS) devices, such as Trench-MOSFETs. Interface state densities (D_IT) of 1_*10¹¹ cm^-2 eV^-1 under flat band conditions were determined using the hi-lo CV-method [1]. Furthermore, current-electric field strength (IE) measurements have been performed and are discussed. Trench-MOS structures exhibited dielectric breakdown field strengths up to 10 MV/cm.