Papers by Keyword: MOSFET

Abstract: A laser slicing technique is an attractive alternative to grinding for thinning SiC wafers. This method has the potential to enable the reutilization of SiC wafers and reduce the waste generated during the grinding process. This paper comprehensively investigates the technical feasibility of laser slicing for the fabrication of SiC power devices. SiC JBS samples fabricated with laser irradiation revealed that by selecting the appropriate laser conditions, we can employ the technique without adversely affecting the JBS leakage current characteristics. Additionally, we fabricated SiC MOSFETs through wafer thinning using the laser slicing technique. The key electrical characteristics of the MOSFETs, including I_GSS, I_DSS, V_th and V_DS(on), showed no differences compared to those fabricated using conventional grinding. These results indicate that laser slicing is a highly promising thinning technique for the fabrication of SiC power devices.

Abstract: Cumulative heavy-ion irradiation effects were investigated in a commercial 4H-SiC double trench MOSFET through a combination of cyclotron experiments and TCAD simulations. Devices were exposed to continuous ¹²⁴Xe³⁵⁺ ion strikes at a linear energy transfer (LET) of 63 MeV·cm²/mg under drain biases from 100 to 400 V. Experimental results revealed the onset of permanent drain and gate leakage at voltages as low as 200 V, with degradation rates increasing by several orders of magnitude at higher bias. Post-irradiation measurements confirmed trench oxide rupture and source leakage path formation, establishing single-event leakage current (SELC) as the dominant degradation mechanism. In contrast, TCAD simulations of isolated ion strikes predicted catastrophic single-event burnout (SEB) only at or above 250–300 V, highlighting the critical role of cumulative damage processes that are not captured in single-strike models. These findings demonstrate that permanent leakage-driven degradation effectively extends the SELC zone beyond conventional SEB thresholds, reducing the safe operating area of trench-based SiC MOSFETs. The results have significant implications for derating strategies in space applications, where current SEB-focused guidelines may underestimate vulnerability, and highlight the need for radiation-hardening by device design to ensure long-term reliability.

Abstract: In this work, we demonstrate a novel oxidation-free gate oxide process consisting of a two-step surface preparation treatment, followed by atomic layer deposition of SiO₂ and a post-deposition anneal in nitrogen. The surface treatment includes a 1300°C anneal in hydrogen and dilute silane, followed by decoupled plasma nitridation (DPN). Long channel MOSFETs fabricated with this process show a 1.5X improvement in peak field effect mobility compared with devices utilizing a standard thermal oxide and NO anneal. The MOSFETs had a positive threshold voltage, low gate leakage, and a breakdown field of nearly 10 MV/cm.

Abstract: In this paper, we study high-temperature H₂, N₂, and H₂/N₂ surface conditioning processes prior to the SiO₂ deposition as a promising approach for SiO₂/4H-SiC interface preparation in metal-oxide-semiconductor field-effect transistors (MOSFET). A thorough electrical analysis is presented, consisting of temperature-dependent transfer characteristics as well as reliability studies regarding bias temperature instabilities (BTI) and dielectric breakdown behavior. Especially N₂-containing surface pretreatments were found to greatly suppress electron traps, whereas hole trapping is enhanced. Finally, X-ray photoelectron spectroscopy (XPS) was utilized to elucidate the elemental surface composition after the different annealing procedures. The obtained results are in good agreement with the electrical characterization and complement already published results regarding the formation of surface reconstructions on 4H-SiC through H₂ and H₂/N₂ annealings.

Abstract: The increased demand for SiC power MOSFETs requires gate dielectrics with low defect densities and high reliability under high electric field and temperature conditions. In this work, we examine how oxidant chemistry and deposition temperature affect the electrical properties of Al₂O₃/SiO₂ bilayer dielectrics formed in n-type 4H-SiC MOS capacitors. These structures consist of a thin SiO₂ interfacial layer, over which Al₂O₃ is deposited via ALD using three different oxidants at a temperature of 150–350°C. C–V and temperature-dependent I–V (25–150°C) measurements show that the choice of oxidant influences the flat band voltage shift and leakage current density, with a process-dependent trade-off between optimizing each parameter. These findings highlight that precise control of oxidant chemistry during ALD is essential for balancing flat band voltage stability with leakage suppression, and that multilayer-specific conduction models are critical for accurately predicting high electric field leakage characteristics in advanced SiC gate stacks.

Abstract: This paper reports on the comparative analysis of several 6.5 kV-rated 4H-SiC Junction Barrier Schottky integrated MOSFETs (JBSFETs) and 4H-SiC MOSFET to assess their forward conduction, 3^rd quadrant behavior, and blocking characteristics. Among different JBSFET architectures, the Island P+ JBSFET achieved nearly identical specific on-resistance (R_on,sp) to the nominal MOSFET while delivering superior 3^rd quadrant conduction and maintaining a high breakdown voltage. Further optimization of Schottky width demonstrated a trade-off between leakage suppression and 3^rd quadrant conduction efficiency that underscores the Island P+ JBSFET’s potential as a reliable high-voltage SiC power device for next-generation applications.

Abstract: Silicon carbide (SiC) has emerged as a leading material for high-power applications. However, the high density of interface states (D_it) at the SiO₂/SiC interface still constrains the performance and reliability of MOSFET devices. In this work, lateral 4H-SiC MOSFETs subjected to post-deposition annealing (PDA) in nitric oxide (NO) of different durations were investigated through capacitance-voltage measurements, supported by an analytical model and an iterative MATLAB-based D_it extraction algorithm. The results demonstrate that NO PDA effectively reduces D_it not only near the conduction band edge but also towards the valence band, yielding improved channel mobility (µ_FE) and enhanced threshold voltage stability.

Abstract: This paper presents the fabrication and characterization of a cell-to-cell integrated SiC lateral bi-directional MOSFET (L-BiD-MOSFET), with blocking performance analyzed through correlation of experimental results and 3D TCAD simulations. The fabricated devices exhibit a breakdown voltage of 600 V, notably lower than the 900 V predicted by 2D simulations. To address this discrepancy, 3D TCAD simulations were performed, which identified electric field crowding at the finger edges as the dominant factor limiting the breakdown voltage. To mitigate this effect, an extended P-top edge design was introduced, which increases the simulated breakdown voltage by more than 10%. Experimental results on devices incorporating the proposed design confirm improved breakdown capability, demonstrating good agreement with simulations. These results highlight the importance of accurate 3D simulation for edge effects in lateral structures. Overall, the proposed design strategy provides valuable guidance for the development of high-performance lateral bi-directional SiC power devices.

Abstract: A body diode is commonly employed as a free-wheeling diode to reduce costs of SiC components instead of an external Schottky barrier diode. However, one of the key issues is higher reverse recovery loss due to bipolar charge contribution to reverse recovery charge. In this study, we investigated the impact of high-temperature annealing on the characteristics of MOSFETs as a cost-effective approach to introduce minority carrier lifetime killers. The trap densities of Z_1/2 center and EH_6/7 center can be controlled by activation annealing temperature. Q_rr of 1900°C measured at 150°C was significantly decrease by 67% compared to that of 1750°C attributed to the 89% suppression of Q_BIP. However, reverse leakage current increased adversely with the activation annealing temperature. R_on and V_th increased with the activation annealing temperature. The trade-off of the annealing temperature worsened slightly compared to that of the doping concentration. It is still possible that high-temperature annealing represents a cost-effective approach to improve the reverse recovery characteristics of the body diode.

Abstract: Paralleling SiC MOSFETs in high-power modules introduces overvoltage and oscillation risks due to parasitic capacitances and inductances. This study presents a 200 kW EV inverter module co-designed at the device and packaging level to ensure switching reliability under harsh automotive conditions. At 800 V, the planar SiC MOSFET maintained stable gate voltage, while a benchmark trench device module experienced severe ringing and failure. Kelvin-source structures and internal gate resistors mitigated parasitic turn-on, and device-level optimizations—including a 0.5 µm foundry technology, silicide gate, and hexagonal cell layout—improved body-diode performance, together with the channel mobility, blocking voltage, and minimized on-resistance and switching losses. The resulting AEPR25B12C1STJN module demonstrated effective resonance damping, matched the performance of commercial trench module FS03MR12A6MA1B in static and dynamic tests, and achieved 98% AC efficiency with over 200 kW output at 150 °C junction temperature.