Papers by Keyword: MOSFET

Abstract: We investigated single photon sources (SPSs) in 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) by means of confocal microscope techniques. We found SPSs only in 4H-SiC/SiO₂ interface regions of wet-oxide C-face MOSFETs. The other regions of MOSFETs such as source, drain and well did not exhibit SPSs. The luminescent intensity of the SPSs at room temperature was at least twice larger than that of the most famous SPSs, the nitrogen-vacancy center, in diamond. We examined four types of C-face and Si-face 4H-SiC MOSFETs with different oxidation processes, and found that the formation of the SPSs strongly depended on the preparation of SiC/SiO₂ interfaces.

Abstract: In this work, TCAD modeling of a 1200 V SiC MOSFET is presented. The main focus is on modeling of the channel mobility, and the Coulomb scattering by interface traps and surface roughness are therefore included. For the Coulomb scattering, the interface trap profiles have been extrapolated from the subthreshold characteristics at room temperature, whereas the scattering due to surface roughness has been fitted by comparing to the transfer characteristics at high gate bias. A comparison with measurements for the transfer characteristic and the output characteristic is also presented. Results show that the reduction of the threshold voltage with increasing temperature and the temperature dependence of the output characteristics are properly modeled.

Abstract: For the paper, we studied how bias stress interruption and reapplication influences threshold voltage (V_T) drift results in SiC DMOSFETs during 175°C bias-temperature instability (BTI) tests. Bias interruptions of even short durations were found to result in significant loss of observed V_T drift, although reapplying the stress bias for a short time immediately before making the post-stress measurement resulted in a significant recovery of the lost drift. The fractional V_T drift (i.e., the ratio of “observed” to “actual” drift) was found to behave similarly to the case of 25°C bias stressing, with an apparent empirical relationship relating to the square of the reapply time, divided by interrupt time. Although questions of bias-stressing at high temperature with room-temperature measurement remain unresolved for now, these results continue to support the feasibility of stress bias reapplication to counteract the loss in V_T drift due to delays or interruptions between stressing and measurement (which are a practical limitation imposed by the necessities of batch testing for qualification in a production environment).

Abstract: A correlation between field effect mobility and an accumulation conductance has been investigated at 4H-SiC MOS interface with barium. 4H-SiC n-channel MOSFETs and n-type MOS capacitors were fabricated with a barium-introduced SiO₂ and a conventional dry SiO₂. The field effect mobility was enhanced by introducing the barium-introduced SiO₂. It is found that there is a linear correlation between the mobility and the accumulation conductance. The MOS interface of the barium-introduced SiO₂ had a lower interface state density of 2×10¹¹ cm^-2eV^-1 than that of the conventional dry SiO₂.

Abstract: The effect of a gate trench bottom p⁺ region (BPR) on the dynamic characteristics of 4H-SiC double-trench MOSFETs was investigated. Although employing a BPR led to an improved trade-off in the static characteristics, a BPR adversely affected the switching characteristics in spite of a reduction in the Miller capacitance compared to the case without a BPR_. Simulation analysis revealed that a resistance between a BPR and a source electrode led to an increase in the switching loss. We have found reduction of the resistance is insufficient in order to provide benefits from the BPR. Hence, it is necessary to improve layouts of contacts of the BPR to the source electrode.

Abstract: In this study, the influence of the gate-source voltage on the forward conduction properties of the body-diode in SiC-MOSFETs is demonstrated experimentally and analyzed by numerical simulations. Thereby, it can be figured out that the conduction properties of the body-diode strongly depend on the operational state of the MOS-capacitor. In depletion case, the current via the body-diode is dominant, whereby in accumulation and inversion mode the current mainly flows through the MOS-channel.

Abstract: An optimized layout for a trench-gate SiC-MOSFET with a self-aligned Bottom P-Well (BPW) was investigated for reduction of the specific on-resistance and switching loss. The static and dynamic characteristics of trench-gate MOSFETs with lattice and stripe in-plane structures were evaluated by varying the distance between neighboring BPWs (d_BPWs). For the stripe structure, more significant improvements on the specific on-resistance (R_on,sp), gate-source threshold voltage (V_th) were achieved compared with the lattice structure, which was found to be due to the difference in the spread of the depletion layer and the channel planes in the device.

Abstract: External Schottky barrier diodes (SBDs) used as free-wheel diodes should be larger in higher voltage devices to avoid bipolar degradation consequent on current conduction of body diodes in SiC MOSFETs. By embedding an external SBD into an SiC MOSFET, we achieved compact 3.3 kV and 6.5 kV SiC MOSFETs that are free from bipolar degradation. The active area of the 3.3 kV/6.5 kV samples is only about a half/quarter of the total active area of a conventional MOSFET and a coupled external SBD.

Abstract: In this paper, near interface traps (NITs) in lateral 4H-SiC MOSFETs were investigated employing temperature dependent transient gate capacitance measurements (C-t). The C-t measurements as a function of temperature indicated that the effective NITs discharge time is temperature independent and electrons from NITs are emitted toward the semiconductor via-tunnelling and/or trap-to-trap tunnelling. The NITs discharge time was modelled taking into account also the interface state density in a distributed circuit and it allowed to locate traps within a distance of about 1.3nm from the SiO₂/4H-SiC interface.

Abstract: In this paper, we present our latest results on 650 V 4H-SiC DMOSFET developments for dual-side sintered power modules in electric drive vehicles. A low specific on-resistance (R_sp,on) of 1.8 mΩ⋅cm² has been achieved on 650 V, 7 mΩ 4H-SiC DMOSFETs at 25°C, which increases to 2.4 mΩ⋅cm² at 150°C. For the first time, the DMOSFET chip is designed specifically for use in dual-side soldering and sintering processes, and a 650 V, 1.7 mΩ SiC DMOSFET multichip half bridge power module has been built using the wirebond-free assembly. Compared to a similarly rated Si IGBT module, the conduction and switching losses were reduced by 80% and ~50%, respectively.