Papers by Keyword: MOSFET

Abstract: In this work, the power cycling capability of discrete SiC MOSFETs of seven manufacturers is investigated. The results show that even nominally similar devices can exhibit substantially different power cycling capabilities. The differences among the tested devices involve the scaling factor and the slope of the lifetime curves, but also the dependence of the baseline temperature. Furthermore, some devices exhibit a considerable increase in power cycling performance towards lower temperature swings, which cannot be characterized properly by power cycling tests at typical test conditions with much larger temperature swings. Thus for a proper assessment of the power cycling performance, multiple tests at suitable test conditions are necessary to obtain meaningful results.

Abstract: MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) technology has evolved rapidly in response to the demand for increased performance, lower power consumption, and ongoing device downsizing. This study provides a comparative review of various materials used in MOSFETs from 2021 to 2025, focusing on developments in channel ^materials as well as their features, advantages, and problems. While silicon (Si) and silicon-germanium (SiGe) continue to dominate mainstream technology, new materials such as indium gallium arsenide (InGaAs) and gallium nitride (GaN) have gained popularity. They are used for high-speed, low-power, and power electronics applications due to their superior electron mobility and high breakdown voltages. Two-dimensional (2D) materials like molybdenum disulfide (MoS₂) and black phosphorus (BP) show promise for ultra-thin, flexible, and energy-efficient devices. However, integrating them into large-scale manufacturing remains a challenge. Silicon is included into transistors, integrated circuits, and solar cells. SiGe excels in high-speed wireless transmission. GaN powers devices with high frequency and voltage, such as LEDs. SiC improves EV and renewable energy systems. InGaAs is essential for near-infrared photodetectors. Diamonds improve electronic cooling. MoS₂ supports field-effect transistors and photodetectors. This article also looks at continuing research into germanium (Ge) and other new materials, which have great mobility but suffer from leakage currents and fabrication complexity. The comparison of these materials provides insight into the future of MOSFET technology, helping researchers and industry professionals to next-generation semiconductor solutions.

Abstract: This study optimizes 28 nm planar MOSFET technology to reduce device leakage current and enhance switching speed. The specific aims are to decrease subthreshold swing (S.S.) and mitigate drain-induced barrier lowering (DIBL) effect. Silvaco TCAD software is used for process (Athena) and device (Atlas) simulations. For the further development of MOSFET technology, we implemented our device (planar 28 nm n-MOSFET) with high-k metal-gate (HK/MG), lightly doped drain (LDD), multi-spacers, and silicide. Simulation validation shows improvements over other 28 nm devices, with lower static power consumption and notable optimizations in both S.S. (69.8 mV/dec) and DIBL effect (30.5 mV/V).

Abstract: This study evaluates the performance and reliability of SiC n-and p-MOSFETs across a temperature range from room temperature up to 400°C, focusing on field effect (FE) mobility and threshold voltage variations under high thermal and bias stress conditions. By analyzing the variations in field effect mobility and threshold voltage under different stress conditions, our study illustrates distinct behaviors between devices with thermally grown oxides and those with chemical vapor deposited (CVD) oxide layers, underscoring significant differences in long term performance. Results indicate that while n-MOSFETs maintain threshold voltage shifts below 3% and exhibit robust characteristics up to 400°C, p-MOSFETs exhibit permanent threshold voltage shifts of up to 10% and mobility reductions of 15% particularly above 300°C DC stress. The 2 nm ultrathin thermal (UT) followed by 40nm CVD SiO₂, outperform thermal oxides, sustaining less degradation in mobility and less shift in threshold voltage under bias temperature instability (BTI) conditions at voltages up to ±25V and temperatures as high as 400°C. This research advances SiC CMOS technology by confirming that SiC n-MOSFETs are ready for high-temperature circuit applications, while highlighting the need for further improvement in p-MOSFETs to enhance their reliability under extreme conditions.

Abstract: Bipolar degradation is a well-known issue when using body diodes in SiC-MOSFETs. Recent studies suggest that H⁺ (proton) implantation can effectively inhibit this degradation, but demonstrations on its suppression are still limited. Therefore, in this study, we have experimentally demonstrated how the expansion of Shockley-type stacking faults (SSFs) is suppressed by proton implantation. We fabricated a vertical SiC-MOSFET, in which protons were implanted into the middle depth of the drift layer. We then subjected the body diode to continuous current stress and performed photoluminescence (PL) analysis. Detailed PL image and emission spectral analysis of SSFs revealed that the proton-implanted layer can function as a recombination-enhancing layer during bipolar operation. Furthermore, it can be formed at any depth within the drift layer by controlling the energy, offering a significant advantage in the design of SiC-MOSFETs.

Abstract: Several 1.2kV 4H-SiC devices of various cell architectures have been successfully fabricated by employing different P+ implantation conditions, resulting in varying levels of Basal Plane Dislocation (BPD) densities across the different device designs. It was found that by utilizing devices designed with an orthogonal P+ source layout as opposed to the traditional P+ stripe pattern, the long-term reliability under sustained 3rd Quadrant current stress conduction can be greatly improved even in devices with medium BPD densities. In addition, the use of the unipolar current of the JBSFET can further enhance long-term reliability under sustained 3^rd Quadrant current stress by mitigating stacking fault expansion, even in devices with a high BPD density.

Abstract: Electrical Wafer Sorting (EWS) on 12 000, 650 V SiC MOSFETs devices from 7 wafers of 200 mm 4H-SiC are compared with electrical deviations and defectivity of initial epitaxial layers measured using Charge biased non-Contact Voltage imaging, QUAD (Quality Uniformity And Defects), and optical surface detection with PL-imaging, respectively. We successfully demonstrate an increased prediction rate in both KR (kill-ratio) and YI (yield-impact) compared to conventional PL-imaging. It is also shown that QUAD not only supplements PL-imaging but supersedes it predicting failure in some electrical test conditions. We therefore show that the combination of QUAD and PL-imaging results significantly improves the accuracy of device failure prediction by uniquely locating faults in the wafers, and thus, improving foresight of successful device fabrication.

Abstract: A novel topological layout was developed to enhance the channel density of 1.2kV 4H-SiC MOSFETs. The innovative "Ladder" MOSFET incorporates an additional JFET and channel region, arranged orthogonally within the layout. To ensure a fair comparison, identical design rules were applied to both the Nominal and Ladder MOSFETs, resulting in calculated channel densities of 0.30 and 0.41, respectively. Comparative analysis was conducted using Synopsys Sentaurus TCAD simulations, where three dimensional (3D) structures for both designs were generated under the same implantation and process conditions, followed by simulations of static electrical characteristics. The results indicate that the Ladder MOSFET achieved approximately 10% reduction in specific on-resistance (R_on,sp) compared to the Nominal MOSFET. Both MOSFET designs were subsequently fabricated, packaged, and evaluated, with the Ladder MOSFET demonstrating a 12.94% reduction in R_on,sp when comparing the best-performing devices from each design.

Abstract: GE Aerospace is developing a novel fabrication method for >3.3 kV devices using ultra-high energy deep implantation and epitaxial overgrowth. We report succesful fabrication of the world’s first 3.5 kV SiC SJ deep implanted junction barrier Schottky (JBS) diodes and 5 kV SiC SJ deep implanted MOSFETs, which exhibit record low specific on-resistance (Ron,sp) and superior breakdown voltages. This innovative method offers a scalable path towards more efficient medium-voltage converters, outperforming traditional SiC unipolar devices.

Abstract: This paper presents the development and optimization of a 1.2 kV Silicon Carbide (SiC) Trench MOSFET with a Bottom P-well (BPW), designed to achieve a compact structure and a simplified fabrication process. By performing the BPW implant before the trench etching process and utilizing it in conjunction with a shallow trench, the process complexity was reduced while maintaining effective corner coverage of the trench gate. Comprehensive simulations and unit process analyses were conducted to evaluate the effects of the hard mask sidewall angle, P-well, and JFET implant doses on device characteristics. Optimal performance was achieved by introducing an additional P+ implant in the P-well region, which significantly enhanced breakdown voltage without affecting channel properties. The optimized device demonstrated a specific on-resistance (R_on,sp) of 2.2 mΩ·cm², a breakdown voltage (BV) of 1600 V, and a threshold voltage (V_th) of 3 V, with potential further reductions in R_on,sp through substrate thinning.