Papers by Keyword: MOSFET

Abstract: In this paper, the performance in 3^rd quadrant operation of 3^rd and 4^th generation SiC power MOSFETs have been evaluated. These are the Gen-3 1.2 kV & 18 A Planar SiC MOSFET, Gen-3 1.2 kV & 19 A Asymmetrical Trench SiC MOSFET, Gen-4 1.2 kV & 26 A Symmetrical Double-Trench SiC MOSFET and Gen-4 1.2 kV & 19 A Trench-Assisted Planar SiC MOSFET. Further, the transients of early-stage degradation development are investigated by conducting continuous stress current thorough body diode of the aforementioned devices to explore the extent of degradation in the body diodes of SiC MOSFETs. These devices are compared to provide a better understanding of the impact of different structures.

Abstract: In this study, we investigated a trench-gate silicon carbide metal-oxide-semiconductor field-effect transistor (SiC-MOSFET) edge-termination structure using an oxide film along the trench surface to simplify the manufacturing process. The trench structure in the termination region serves as a guard ring, eliminating the need for a separate guard ring process and thereby reducing the number of process steps. To suppress electric field concentration at the edge of the cell region under high voltage, a boundary region between the cell and termination regions was implemented. Technology Computer-Aided Design (TCAD) device simulations confirmed that by using the boundary region and narrowing the mesa width, avalanche breakdown was prevented up to the breakdown voltage of the cell region.

Abstract: This paper investigates the charge balancing and performance optimization of two 1.2 kV rated Semi-Superjunction (SSJ) MOSFETs. Beginning with a conventional double trench MOSFET, SJ trenches are imposed in 2D (within the X-Y plane unit cell) and in 3D (trenches in Z-Y plane, perpendicular to the gate trench). The optimization of these structures focuses on the effects of p-pillar doping, tilt angle, and z-plane pillar width and the trade-off between specific on-resistance R_on,sp, breakdown voltage (BV), implantation window, and gate reliability is assessed for each configuration. The 2D SSJ MOSFET, is the device that offers the highest breakdown voltage of those assessed (1781 V) and the widest implantation window (±25.4%), when implemented with a vertical trench sidewall, while this is a trade-off against achieving the lowest R_on,sp​, (1.15 mΩ.cm²) with a 12.5° side wall angle. In the 3D SSJ MOSFET, a reduced p-pillar depth in the z-dimension, and hence a higher doping density, leads to a significant improvement in R_on,sp. The Z-plane p-pillars in the 3D device efficiently deplete its JFET region, causing the R_on,sp of the 3D devices to be higher than the 2D devices, and the breakdown voltage lower. However, this also results in very low electric field (<0.5 MV/cm), in the gate oxide, offering a safe alternative to the 2D devices (1.69 MV/cm). Differences between the devices could be narrowed in the future with optimal JFET design.

Abstract: We investigated how proton implantation influences electrical characteristics of the 4H-SiC MOSFETs. Bipolar degradation in SiC is one of the key issues to be solved for utilizing the bipolar operation in SiC power devices. Its suppression with the proton implantation technique has recently been reported. If we can apply such a new technique being involved for realizing reliable SiC MOSFETs, it would give us great merit to take advantage of the body diode. However, few study has been reported of proton implanted SiC MOSFETs, to our knowledge. Thus, we fabricated 4,000 chips, applied current stress to their body diodes and subsequently evaluated them to verify statistically any effectiveness on the suppression of the bipolar degradation as well as on the electrical performance of MOSFET in order to consider its technological applicability to their mass production process. We found that proton implantation not only has little influence on the static electrical characteristics of the MOSFETs but also improves the switching characteristics.

Abstract: In this paper, the effects of various proton irradiation energies and doses on the electrical characteristics of SiC MOSFETs have been evaluated and characterized using a proton accelerator. The devices under test were designed, fabricated and packaged using 1.2 kV/0.6 µm-tech SiC MOSFET processes. The results demonstrate that the threshold voltage (V_th) of the irradiated devices shifted towards negative values due to the radiation-induced positive oxide trapped charges. Moreover, this negative shift in V_th and positive trapped charges of field limiting ring (FLR) oxide led to an increase in output currents and a reduction in the breakdown voltage values.

Abstract: In this study, we numerically compare the characteristics of Si and SiC CMOS operational amplifiers (OpAmp) using LTspice. According to prior researches, we set the device parameters for Si and SiC MOSFETs. The OpAmp consists of three stages: the input stage, the gain stage, and the output stage. We established three criteria for the OpAmp's operation: (1) a unity gain frequency of 1MHz, (2) an open-loop gain of at least 75dB, and (3) a phase margin of more than 60° when a load capacitance is 300pF. To achieve a unity gain frequency of 1MHz, we adjusted the values of the resistor and capacitor used for phase compensation. The supply voltage was set to be ±5V for the Si OpAmp and ±15V for the SiC one. Our numerical analysis of the frequency response shows that the Si OpAmp met all three criteria. In contrast, the SiC OpAmp, when faced with a load capacitor of 300pF, had a phase margin of 43.4°, falling below the 60° mark. For the SiC OpAmp, the frequency response declined rapidly when the supply voltage dropped to 10V or below.

Abstract: SiC MOSFETs still suffers from some open issues, such as the high density of defects existing at the SiC/ SiO₂ interface. In order to characterize such interface, a non-destructive investigation technique should be employed. In this work, we investigate the measurement of Gate capacitance with biased Drain. More in detail, the effect of frequency on such curves is considered. The analysis is performed using both in experimental setup and numerical framework. Experimental and numerical results both exhibit a sharp capacitance peak in the inversion region which reduces its height as frequency increases.

Abstract: For a reliable MOSFET performance it is crucial to identify and reduce device performance limiting 4H-SiC/SiO₂ interface defects. Previous studies have focused on the quantification of the interface states density, however, the atomic defect structure is still to be investigated. Here, we introduce a new approach based on opto-electrical measurements, which allow to determine the energetic position of interface defects. The measurement routine is performed at cryogenic temperatures to suppress the thermal emission of electrons, which were trapped at interface states during the cooldown processed (from 300 K to 15 K) while a positive gate voltage of 50 V was applied. At 15 K the photon-assisted emission of trapped electrons is measured in dependence on the photon’s energy (1.8 eV-3 eV). The reduction of the threshold voltage is taken as an indicator for the amount of released charges after each photon irradiation. We found an enhanced emission efficiency at certain photon energies, especially at 2.8 eV. Near-interface-traps (NITs), reported by Afanasev et al. are located close to the measuredtrap level with E_NIT = E_{C, SiO2}−2.77(5) eV. Recently, El-Sayed et al. suggested wide-angle O-Si-Obonds as defect configuration, that act as electron traps and have a similar energy as the measure traplevel.

Abstract: This article presents an innovative approach to achieve a high channel mobility for 4H-SiCp-MOSFET via dielectric-semiconductor interface engineering involving atomic layer deposition(ALD) of ultrathin B₂O₃ and SiO₂ stacks. The application of ultrathin boron oxide via ALD introducesa highly manufacturable solution for the passivation of SiC interface. The interface states near valenceband reduces the channel mobility for SiC p-MOSFETs and increases the threshold voltage. Theintroduction of ultrathin B₂O₃ interlayer reduces the threshold voltage and improves the field effectmobility to 12.60 cm²/Vs while the p-MOSFET without the interlayer provides the mobility of 8.91cm²/Vs. This work also includes the optimization of the post-deposition annealing (PDA) conditionsspecific to ultrathin B₂O₃ and bulk SiO₂ dielectric stack to obtain high field effect channel mobilityfor SiO₂/SiC p-MOSFETs.

Abstract: Effective control of device geometry is key to mitigating high localized electric fields in next-generation SiC power devices. Advanced trench processing allows for highly tunable trench-gate architectures in trench MOSFETs. By utilizing a two-step inductively coupled plasma reactive ion etch (ICP-RIE) process, a high degree of trench base corner rounding can be achieved, irrespective of trench opening corner geometry prior to post etch treatments. Sentaurus TCAD device modelling highlights the importance of effective electric field dispersion at the gate oxide using rounded trench corners, while I-V characterization of fabricated trench MOS-capacitor devices demonstrate the influence of trench base corner rounding on gate oxide breakdown.