Papers by Keyword: Metallic Contamination

Abstract: This presentation focuses on semiconductor wafer cleaning technology, one of the most critical technologies in semiconductor device manufacturing for obtaining high yield and reliability, and discusses the past, present, and future of the technology. Emphasis is placed on the review of contamination control and cleaning technologies in the early days since the invention of the transistor. To celebrate the 30+1-year anniversary of the UCPSS, a review will be given of both the first conference held in Leuven in 1992 and the second one held in Bruges in 1994. There will be more research challenges and business opportunities in environmentally benign, innovative damage-free wafer cleaning and surface preparation technologies for future applications.

Abstract: This paper offers a preliminary study for the analysis of metallic contamination on front-end patterned wafers obtained by two different techniques based on the etching of the whole patterns, LPD-Bulk and VPD-Bulk coupled with an ICPMS. To elaborate the analysis of patterned wafers, methods were first verified and optimised on reference Si wafers. Both techniques are complementary methods for the etching of wafers. LPD-Bulk enables a fast etching of several micrometres of Si but with less precision than VPD-Bulk, which is more adapted for the etching of layers thinner than 1 micrometre. The intentional contamination in SC1 and H₂O bath of monitoring wafers showed that contamination in H₂O is better controlled due to the absence of chemical reactions, competition between oxidation and etching processes occurring during SC1. And diffusion of contaminants at the tested temperatures from 20°C to 80°C, does not occur. Heat treatment should be applied to allow the diffusion of metallic contaminants in the bulk of the wafers.

Abstract: We have found that to the detection sensitivity of Total reflection X-ray fluorescent spectrometry (TXRF), the total volume of trace particles generated by vapor phase treatment (VPT) must be increased and metal atoms need to be included in the particles. The detection sensitivity for Cu is enhanced by assisting Cu ionization in the liquid drops condensed form the vapor. We consider that since incident and reflected X-rays resonate 30nm from the surface, the total reflection intensity of metals included in the particles is enhanced.

Abstract: We studied the detection by TXRF of several transition metals on the surface of III-V materials for high mobility channel. It has been found that the lower limits of detection of some transition metals on the surface of III-V materials become higher than that on the Si surface because the sum peaks or Raman scattering peaks as well as the fluorescent X-ray main signals from the materials themselves partially cover those from the transition metals

Abstract: challenge. Initiated by copper integration for BEOL interconnects the phenomena expanded with the HK / Metal Gate stack use. Therefore, the backside and bevel cleaning became a key parameter to insure both tools integrity and wafers yield while reducing as more as possible the cross contamination risk. The main parameter to avoid the contamination transfer across all the different clean room equipments is to strictly manage the backside and bevel areas on the wafers. Thus, the use of single side processor tools which achieve the specific treatment of the backside and bevel areas drastically increases. Up to now, diluted-HF mixtures are mainly used in production plants demonstrating a good efficiency to remove contamination on dielectric surfaces. Thus, a very large range of contaminant materials can be addressed with a performance level which has been widely evidenced on BEOL applications as well on more FEOL embedded specific materials (ie: Hf, La, W). Nevertheless, the fundamental mechanism which drives the diluted-HF mixtures efficiency remains only based on a lift-off effect as the contaminant can be caught in the liquid phase after a fixed amount material etching. Most of the time there is no direct solubilisation of the contaminant from the surface. For silicon surface without any dielectric coverage the efficiency of a single diluted HF mixture can be very poor especially towards noble metals contamination. Various on-going developments (ie on MRAM technology or 3D integration or Imagers) in which pure FEOL tools are used on MEOL or BEOL levels required more efficient cleaning towards a larger range of metal contamination on backside and bevel areas.

Abstract: III-V semiconductor compounds are increasingly studied for their interesting properties in the fields of microelectronics, optoelectronics, infrared detectors or solar cells. Firstly, they are promising candidates to replace silicon as a channel material. As CMOS scales beyond the 22 nm node it is widely expected that new higher mobility channel materials such as In_xGa_1-xAs will have to be introduced [1]. On the other hand, III-V materials have a direct bandgap making them useful for optoelectronic devices or high-efficiency multijunction photovoltaic cells. For these applications InP, GaAs and their alloys as In_xGa_1-xAs and Ga_xIn_1-xP are investigated [2]. Depending on the targeted applications, several possible integration routes of III-V components could be considered: from 100 mm III-V substrates to III-V epitaxial layers grown on 300 mm silicon wafers as well as a few square centimetres chips bonded on 200 or 300 mm carrier wafers for photonics applications. In all cases, the manufacturing of devices requires a multitude of wet chemical steps including selective etching steps (from a few nanometres up to several microns) and cleaning steps (metallic or particles contamination removal).

Abstract: The cumulative installed solar power generation has been rising exponentially over the past decade. This has lead to a concomitant rise in production capabilities, leading eventually to excess production capabilities and rapid price declines per unit. In order to compete with the standard electricity generation the cost of solar panel production and installation needs to decrease even further. At the same time the solar panel and cell makers need to be able to keep a healthy margin. A crucial element in this exercise is a close control on the Cost of Ownership (CoO) of a solar cell / panel fabrication site.

Abstract: Contamination control has become a high-centered issue for the fabrication yield, performance and reliability of leading-edge ULSI devices. With the progress of sizing down dimensions in higher-density devices, complicated device structures and various novel electronic materials have been introduced, particularly in the latest devices such as CMOS and nonvolatile memory LSIs (Table I). On the other hand, high productivity is a necessity when you consider QTAT (quick turnaround time) and cost-effective flexible ULSI manufacturing lines. Therefore, effective contamination control coupled with adequate protocol has become essential in such production lines. The point of the protocol is minimization of damage caused by impurity metals diffused from these novel electronic materials [1-5].

Abstract: The monitoring and optimization of wet clean and surface preparation processes is a major challenge in the microelectronics industry [1, 2]. Today, the main methods used in clean rooms are visual inspection by light scattering (principally applied to particle detection) and metallic contamination detection by Total-reflection X-Ray Fluorescence (TXRF). These methods, despite good sensitivity and recent progress [3, 4] are not sufficient, especially considering non-visual defects not measurable by light scattering, nor TXRF due to their chemical nature or to their size and location (TXRF is not applicable to light elements – with Z < 11 – and is typically a 1 cm resolution tool, with 1 to 2 cm edge exclusion). Non-vibrating Surface Potential Difference Imaging (SPDI), introduced in 2005 under the name of ChemetriQ® is an in-line, non-contact, non-destructive inspection technique based on the imaging of surface Work Function (WF) lateral non-uniformities [5]. Recent studies show very promising results for SPDI: high sensitivity to traces of metals on Si wafers with native oxide [6]; fast imaging capabilities of unpatterned or patterned wafers with sensitivity to chemical residues and charge [7, 8]. In this work, the ChemetriQ method is evaluated for in-line control of wet clean processes. The variation of SPDI data from various contaminants is compared to intra- and inter-wafer variations related to the cleaning and measurement conditions. Note that all wafer maps are presented with the notch oriented at 6:00.

Abstract: In the semiconductor industry, the edge exclusion of processed wafers is decreasing to accommodate more integrated circuits. With this trend, there is a higher risk of detrimental contamination at the wafer edge and bevel making the monitoring for metallic contamination in these areas critical. Cross contamination from the edge and bevel can occur at many processing steps. For example, metals can spread from the wafer edge, bevel and backside to the wafer’s surface in a wet cleans process. In immersion lithography, the water drop that is scanned across the wafer could transport contamination from the edge and deposit it across the wafer surface. Contamination on wafer edge and bevel can have many origins; handling systems in every process tool, reaction products in etching, and residuals of new materials in high-k for CVD and PVD, for example. To know what metallic contamination is present, and to investigate the causes are essential for wafer edge control.