Papers by Keyword: Multi-Core

Abstract: This paper is devoted to the numerical computation of a steady-state thermo-fluid modeling related to the Friction Stir Welding Process in a two-dimensional cylindrical geometry. It analyzes the efficiency of the implementation on parallel architectures of two finite-difference schemes on a structured grid. The first one applies the Newton-Raphson method to compute a numerical solution of this non-linear elliptic type equation, and uses an iterative sparse solver. The second one is based on a time-marching approach converging to the steady state solution thanks to a time-explicit computation. Their respective performance is presented and discussed. Some numerical simulation results are presented to validate the proposed approach.

Abstract: Tool path generation for CNC machine tools is mainly responsible for quality, accuracy and productivity of the manufacturing process and therefore in the focus of research activities. Many approaches regarding this topic yield to complex algorithms and thus, demand for the availability of sufficient processing performance realizing this algorithms in a CNC real-time environment. For that reason this paper presents an approach on how to use multi-core processors for CNC tool path generation functions. A partitioning concept is presented allowing to concurrently execute multiple threads realizing interpolation and arc length calculation algorithms. At the example of B-spline interpolation the execution time of the tool path generation function could be reduced significantly using the presented approach.

Abstract: Instrumentation technology has been widely used in debugging interactive applications, such as interactive games and virtual reality. Debug codes are instrumented into a target program in order to collect run-time information. Although instrumentation provides detail information of the target program behavior, it can significantly prolong execution time, change program behavior and lead to incorrect debugging results, especially for time dependent and real-time applications. This paper aims to design a scalable parallel debugging mechanism to reduce instrumentation overhead while collecting detail run-time information. We design a new synchronization mechanism of instrumentation, named MDM, which uses multiple buffers to process debug messages. Also, a binding mechanism is used to specify the relationship between the target program, helper threads and cores. We conduct a case study of augmented reality interactive games on an Intel Core i7-2600 processor with Linux 2.6.38. Compared to existing methods, MDM can reduce instrumentation overhead by up to 19%.

Abstract: With the existence of traditional SOC chip, the encryption and decryption speed and low power cannot meet the computing needs of the modern diversity, then we present a heterogeneous multi-core system which designed based on shared memory on the Xilinx Virtex-5 platform. This paper is in-depth research about heterogeneous multi-core password architecture, static task partitioning, scheduling strategy and the communication mechanism between cores. The three cores systems are designed and builded based on shared memory to realize ZUC algorithm which generates a stream cipher on virtex-5 platform. The three microblaze cores are responsible for inter-core communication, the implementation of ZUC algorithm and articulating IC card to read keys. Through the design of three cores system, give full play to the hardware, software and computer architecture parallelism at all levels to improve the performance of the algorithm to achieve high performance green computing.

Abstract: During real time there are problems in transmitting video directly to the client. One of the main problems is, intermediate intelligent proxy can easily hack the data as the transmitter fails to address authentication, and fails to provide security guarantees. Hence we provide steganography and cryptography mechanisms like secure-code, IP address and checksum for authentication and AES algorithm with secret key for security. Although the hacker hacks the video during transmission, he cannot view the information. Based on IP address and secure-code, the authenticated user only can get connected to the transmitter and view the information. For further improvement in security, the video is converted into frames and these frames are split into groups and separate shared key is applied to each group of frames for encryption and decryption. This secured communication process is applied in image processing modules like face detection, edge detection and color object detection. To reduce the computation time multi-core CPU processing is utilized. Using multi-core, the tasks are processed in parallel fashion.

Abstract: The parallel algorithm of merge sort is proposed. The improvements of merge sort are analyzed in this paper. OpenMP is applied in the proposed algorithm for implementation. The results of complexity and execution time of the proposed algorithm indicate that the parallel algorithm approach the optimal case.

Abstract: Amount of legacy systems in early stages are fall behind multi-core ages, and these legacy systems were designed for single processor which can not expand the computing power of the multi-core hardware. In this paper, we employ aspect oriented programming technology and design the crosscutting concerns for the potentially parallelizable software components of legacy systems. We propose a new multi-core programming model which can change the single thread of legacy systems into multi-threads for multi-core hardware platform without revising the source code of legacy systems. The proposed method can enhance the performance of software and utilization of hardware.

Abstract: This paper designs multi-core and multi-channel physical education (PE) teaching innovation management platform and introduces TIM theory, so as to collect the transmission speed of video signal for different number of nuclei and the number of channels' teaching management platform. It has found from the calculating that, when the nuclear number is 1, and the channel number is 2, the speed of data transmission signal is the lowest, and the theoretical value is 5.6, the measured value is 5.5, namely the theoretical value is consistent with the measured value. When the nuclear number is 4, and the channel number is 8, the speed of data transmission signal is the highest, and the theoretical value is 9.6, the measured value is 9.7, namely the theoretical value also consistent with the measured value. So in the design of PE teaching innovation management platform, it needs to synthetically consider the nuclear number of DSP and the channels number, so as to achieve the effects of optimization design for the teaching management platform.

Abstract: Nowadays, there are two approach in mixed-criticality scheduling. One is reservations-based approach such as EDF-VD(Earliest Deadline First-Virtual Deadline) and the Other is priority-based scheduling such as OCBP(Own Criticality Based Priority). This paper compared the two mixed-criticality scheduling algorithm from three aspects. The simulation results show that EDF-VD is better than OCBP in completed tasks and the system utilization, but in unmissed deadline ratio the later owns the better.

Abstract: Dijkstra’s algorithm is a typical but low efficiency shortest path algorithm. The parallel Dijkstra’s algorithm based on message passing interface (MPI) is efficient and easy to implement, but it’s not very suitable for PC platform. This paper describes a parallel Dijkstra’s algorithm. We designed the parallel algorithm and realized it based on multi-core PC and MPI software platform. The implementation is convenient, and the performance experiment shows that the algorithm has satisfied speedup and efficiency.