Papers by Keyword: Multi-Core

Abstract: Nowadays, wireless sensor networks (WSN) focus on sounds and images and other complex patterns such as data collection, processing, transmission, integration and reconstruction. In order to support these types of data, network node processors need the higher requirements. The embedded multi-core processors are able to play a great role. For improving the efficiency of multi core processing node, a cache allocation algorithm which provides suitable cache to parallel tasks is proposed. By experiment verification, the proposed algorithm achieves higher performance than that adopting conventional LRU scheduling algorithm which improves the WSN performance and utilization effectively.

Abstract: Multi-core processor has been a hot topic since it improves operation speed. It is not easy to get efficient parallel processing data algorithms because of waste of hardware resources. In this paper, a novel multitask parallel algorithm based on getting common substring of two strings is described in order to improve the data-handling capacity of the multi-processor. Firstly, this algorithm performs Task Parallel Library (TPL) in VS.NET, and then schedule the algorithm proposed in this paper to process data. This algorithm is tested by actual parallel data. The results demonstrate that this algorithm overcomes the problem of waste of hardware resource, can take full advantage of the features of multi-core parallel processing data thereby enhancing the parallel speedup, greatly improving the efficiency of data processing.

Abstract: Multi-core processor technology is getting more and more common for both business and private use. However, the operating systems and applications are not keeping the same pace with multi-core hardware. In the mean while, to get better performance, more factors need to be considered under multi-core platform, e.g. load balance, cache, task relationship, etc. This paper focuses on making full use of multi-core processor through scheduling the tasks to proper core with CPU priority Algorithm which calculates a priority of each core when scheduling a task. With CPU Priority, it is easier to take interesting factors into account and combine several factors together. We did our work based on a scheduler simulator implemented with Python and we observed that, with CPU priority scheduling algorithm, it does suggest a flexible way to schedule the CPU assignment and is able to gain some satisfactory improvement on the response performance according to our simulation.

Abstract: To integrate the programming model and the executing model, the procedure is introduced into the design of multi-core micro-architecture, and the method-centric (Metric) multi-core architecture is proposed. A functional simulator for Metric multi-core architecture is designed and implemented. The simulator is implemented with the object-oriented programming methodology, and is composed of three groups of components: functional simulator, ISA emulator and auxiliary components. The experimental results show that the implemented simulator is effective and correct.

Abstract: To improve the flexibility and adaptability of the existing multi-core cipher system, this paper designs a multi-core cipher processing system based on NoC. By enlarging the cipher processing instructions on the RISC architecture, this system ensures the performance and flexibility of algorithms on the multi-core system. In addition, this paper designs dedicated data frames architecture for cipher processing and proposes a assignment partition mechanism for differ-ent application conditions. The system has finished the prototype verification on the platform of FPGA. The result shows that the system can realize the common algorithms flexibly, and the per-formance can reach 1Gbps.

Abstract: This paper introduces a novel implementation of in-vehicle traffic signs and traffic lights recognition system based on FPGA multi-core processers. Images could be processed with multi-core parallel processor using the corresponding relationships of traffic signs’ color and shape. We implement this vehicle vision system on SOPC hardware platform.

Abstract: While the frame rate is higher and the image size is larger, sequence images processing is harder. Good real-time can be ensured by the multi-core DSP in the embedded image processing system. TMS320C6670 which is the multi-core DSP designed by TI corporation is selected as study object. Based on hardware characteristics analyzed, the Data Flow model is adopted as the multi-core processing model. Two data processing subtasks assigning methods are analyzed by comparing their advantages and disadvantages on the system idle time and memory requirements. The data processing subtask assigning flow is design for a serial sequence images processing example. An inter-core data transfer flow design idea is put forward. Using methods and occasion of two kinds of data buffer establishing techniques is studied and defined. An inter-core notification flow design idea is put forward. Using methods and occasion of three notification methods based on the interrupt controller and the Semaphore2 module is studied and defined.

Abstract: To take full advantage of multi-core processor resources, this paper examines the multi-core platform using OpenMP implementation of two kinds of pi parallel algorithms, numerical integration and Monte Carlo. The experimental results show that optimized algorithm with the OpenMP pragmas compared with the serial code has been improved speed significantly, also achieved satisfactory speedup and parallel efficiency that effectively improve the utilization of computer resources of the multi-core, parallel algorithm for the realization of Pi provides a new way of thinking.

Abstract: In this paper, five kinds of typical multi-core processers are compared from thread, cache, inter-core interconnect and etc. Two kinds of multi-core programming environments and some new programming languages are introduced. Thread-level speculation (TLS) and transactional memory (TM) are introduced to solve the problem of parallelization of sequential program. TLS automatically analyze and speculate the part of sequential process which can be parallel implement, and then automatically generate parallel code. TM systems provide an efficient and easy mechanism for parallel programming on multi-core processors. Typical TM likes TCC, UTM, LogTM, LogTM-SE and SigTM are introduced. Combined the TLS and TM can more effectively improve the sequential program running on the multi-core processors. Typical extended TM systems to support TLS likes TCC, TTM, PTT and STMlite are introduced.

Abstract: Multi-core and dataflow architecture recently researched on parallel computing can well satisfy the requirement of high-performance for PLC processors handling program by exploiting parallelism in the program. But the compiler translating the ladder diagram program into the instructions of the architecture has not been yet developed. For the problem, the paper presents a compiler aiming at editing a ladder diagram which is one of programming languages of PLC and then compiling it into instructions of multi-core function-level dataflow architecture. The compiler takes row doubly linked list as internal representation of a ladder diagram, and logic binary tree as intermediate representation during the process of compiling according to similarity of the binary tree to function-level dataflow graph, written in java.