Papers by Keyword: Network-on-Chip (NoC)

Abstract: With further increase of the number of on-chip device, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new structure to solve the interconnection of on-chip device. The paper proposes a network-on-chip dynamic and adaptive algorithm which selects NoC platform with 2-dimension mesh as the carrier, incorporates communication energy consumption and delay into unified cost function and uses ant colony optimization to realize NOC map facing energy consumption and delay. The experiment indicates that compared with random map, single objective optimization can separately saves (30%~47 %) and ( 20%~39%) in communication energy consumption and execution time compared with random map, and joint objective optimization can further excavate the potential of time dimension in mapping scheme dominated by the energy.

Abstract: Traditional ant colony mapping algorithm not only has big power consumption, but also is easy to be trapped into local optimization on NoC mapping, for which the paper proposes an optimization scheme based on improved ant colony algorithm. Firstly, the parameters are for initialization operation. Secondly, tabu list is used to solve them, and the solutions are for local optimization of optimal solutions by using 2-opt algorithm. Lastly, pheromone rules are updated. Simulation experiment indicates that compared with traditional ant colony mapping algorithm, NoC mapping optimization scheme based on improved ant colony algorithm not only has better performance on mapping power consumption, but also is not easy to be trapped into local optimization.

Abstract: In Network-on-Chip (NoC), adaptive routing provides packets multi paths to reach their destinations. Thus, packets can escape the hot-spot nodes. However, as our study indicates that adaptive routing cannot distribute traffic evenly in the network as expected. A local region will be injected more packets than others, which makes congestion takes place in that local region. Local congestion has significant impact on network performance. In this paper, we carry out a detail studying on local congestion in NoC.

Abstract: The widely used routing algorithm performance metric of adaptiveness cannot precisely measure performance of routing algorithm. In this paper, we propose a new metric of routing pressure for measuring routing algorithm performance. It has higher precision of measuring routing algorithm performance than degree of adaptiveness. Performance of routing algorithm can be evaluated through routing pressure without simulation. It can explain why congestion takes place in network. In addition, where and when congestion takes place can be pointed out without simulation.

Abstract: Large scale Multi-Processor System-on-a-chip (MPSoC) based on Network on Chip (NoC) can support multiple applications running simultaneously. When the multiple-application workload includes streaming applications processing massive data, the communication concentrated on shared memory can't be ignored. In this paper, we propose a task assignment strategy for multiple-application workload which includes one streaming application on a NoC-based MPSoC. The proposed algorithm first assigns the streaming application centering the multi-port shared memory, and then assigns the other applications minimizing external communication congestion. By adopting the proposed algorithm, the memory-contention tasks are assigned to the PEs close to the shared memory and the overall congestion is minimized. This allows the system to provide better overall performance.

Abstract: A hybrid MPSoC (Multi-Processor SoC) simulator was proposed in this paper. The simulator provides statistical traffic model and behavior-level model for computation, along with cycle-accurate model on basis of ISS (Instruction-Set Simulator) including ARM and TI DSP. The simulator also provides NoC (Network-on-Chip) and traditional bus for on-chip communication and interconnection. As shown in the case study, the proposed simulator may improve the efficiency of building-up a multi-core simulation platform, and then may be used for simulation and evaluation of the constructed multi-core and NoC architectures.

Abstract: For logic-based distributed fault-tolerant routings, livelock is a troublesome challenge. In this paper, we prove the sufficient conditions which make the fault-tolerant routing PR-WF [1] to be livelock-free. Due to the diversity of fault blocks, it is almost impossible to verify the sufficient condition of livelock-free by a formal method. In this paper, both visual analysis and enumerative simulation methods are taken to prove livelock theorems. In order to avoid livelock, an algorithm is presented to extend fault blocks. Experimental results show that, it has to disable no more than 1.8% no-faulty links to avoid livelock if the true faulty link rate is 10%.

Abstract: Future high-end System-on-chips (SoCs) will be consisted of hundreds of cores integrated on a single chip. On-chip communication becomes the major performance bottleneck of SoCs. Network-on-Chip (NoCs) have become as the most prominent solution to on-chip communication problems. Network topology which affects the total network conformance is basic of network related researches. The objective of topology synthesis is to minimize the power consumption and router resources while satisfying bandwidth constraints. In this paper, we present a two-level genetic-algorithm (GA) based technique to synthesize application-specific NoC topology. Comparing to an existing three-level GA, experiments show that our technique saves 1.8% energy while saving great runtimes of 97.79%. Our technique generates approximate optimal topology less than one minute.

Abstract: Network on Chip (NoC) has been proposed as a new paradigm for designing System on Chip which supports high degree of scalability and reusability. Mapping the IP cores onto a given platform is an important phase of NoC design which can greatly affect the performance and energy consumption of the chip. Mapping which is an instance of the constrained quadratic assignment problem (QAP) belongs to the class of NP-hard problems. Due to the complexity of many of these problems, particularly those of large sizes encountered in most practical settings, meta heuristic algorithms are conspicuously preferable. These algorithms help us achieve optimal or near optimal solutions in large size applications with reasonable time. In this paper eight types of Genetic Algorithms (GA), Particle Swarm Optimization(PSO), Simulated Annealing(SA), Differential Evolution(DE) and Imperialist Competitive Algorithm (ICA) are applied in their basic frameworks for solving the mapping problem on two real core graphs Video Objective Plan Decoder and MPEG-4. The experimental results show the comparisons of these different meta heuristic algorithms with each other.

Abstract: In this paper, we implement and analyze different Network-on-Chip (NoC) designs with Static Random Access Memory (SRAM) Last Level Cache (LLC) and Dynamic Random Access Memory (DRAM) LLC. Different 2D/3D NoCs with SRAM/DRAM are modeled based on state-of-the-art chips. The impact of integrating DRAM cache into a NoC platform is discussed. We explore the advantages and disadvantages of DRAM cache for NoC in terms of access latency, cache size, area and power consumption. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under different workloads, the average cache hit latencies in two DRAM based designs are increased by 12.53% (2D) and reduced by 27.97% (3D) respectively compared with the SRAM. It is also shown that the power consumption is a tradeoff consideration in improving the cache hit latency of DRAM LLC. Overall, the power consumption of 3D NoC design with DRAM LLC has reduced 25.78% compared with the SRAM design. Our analysis and experimental results provide a guideline to design efficient 3D NoCs with DRAM LLC.