Papers by Keyword: On-Resistance

Abstract: A comparative study of state-of-the-art commercial 1200V trench-gate, planar-gate, and trench-assisted planar Silicon Carbide (SiC) MOSFETs is presented. The experimental study mainly focuses on disclosing the static and robustness characteristics of distinct SiC technologies targeting automotive applications under room and high temperatures. The benchmark study of static characteristics covers specific on-resistance (R_ON,SP), gate leakage (I_GSS​), drain leakage (I_DSS​), breakdown voltage (BV_DSS​), and drain-induced barrier lowering (DIBL) effects. The avalanche robustness is investigated by the unclamping inductive switching (UIS) setup under 25 °C and 175 °C while the single-pulse and repetitive short-circuit capability is evaluated under hard switching fault (HSF) under 25 °C.

Abstract: The SiC trench gate MOSFET with narrow cell pitch is demonstrated using a process in which the n⁺ source is self-aligned to the trench gate. A minimum cell pitch of 1.6 μm, which is difficult to achieve using the conventional device structure, is easily fabricated by applying a deep n⁺ source and a buried interlayer dielectric structure. The cell pitch reduction indicates a beneficial trend that contributes to a decrease in the specific on-resistance and an increase in the breakdown voltage. The process and structure are promising for further improving SiC power device characteristics.

Abstract: Experimental results from 15 kV-rated SiC DMOSFETs developed by GeneSiC Semiconductor are presented. A breakdown voltage of 16.7 kV is recorded, with < 200 nA leakage current at 15 kV. R_DS,ON in the range of 4-5 Ω, 12-15 Ω or 50-75 Ω were measured on MOSFETs with chip sizes of 25 mm², 16 mm² and 9 mm², respectively, with a lowest specific R_DS,ON of 238 mΩ-cm². The impact of MOSFET channel length and JFET width on the device performance is elucidated. Single-pulse avalanche energy = 22.1 J/cm² and t_AV=18.2 μs is achieved. V_G-+20 V gate stress applied at 175°C showed good V_TH stability with only a small 200-300 mV increase during the initial stages of the stress time.

Abstract: In this paper, 4H-SiC planar MOSFETs were designed and fabricated. By using TCAD tool, the trade-off between on-resistance and maximum gate oxide electric field was optimized. With optimized gate oxide growth process, the gate oxide’s critical electric field of 9.8 MV/cm and the effective barrier height of 2.57 eV between SiO₂ and 4H-SiC were obtained. The field effective mobility with different p-body doping was compared and studied. The MOS interface state density of 1.12E12 cm^-2eV^-1 at E_C - E_IT = 0.21 eV and channel mobility of 19.3 cm²/Vs at V_GS = 20 V were obtained. The fabricated MOSFET’s on-resistance of 6.4 mΩcm² was obtained with hexagonal cell structure which is very consistent with the simulation results.

Abstract: Silicon carbide (SiC) MOSFET features low on-resistance per area even at high temperatures compared to a silicon (Si) counterpart with the same voltage rating. However, SiC MOSFET exhibits a unique behavior over operating temperatures due to the presence of interface trap charges. The effect of temperature on the on-resistance of SiC MOSFET has been studied through experimental measurements at difference temperatures from - 30 °C to 150 °C. The results show that high contribution of channel resistance is the critical factor to determine the behavior of SiC MOSFET with temperature.

Abstract: Power MOSFETs operate at elevated temperatures due to self-heating and hot ambient temperatures. This paper analyzes the increase in on-resistance with temperature for 1.2 kV rated 4H-SiC planar MOSFETs. The impact of various structural parameters are studied using analytical models supported by experimental data. This work defines how to achieve a low ratio [R_on(150°C)/R_on(25°C)] by structural optimization of 1.2 kV SiC planar MOSFETs for the first time. It is found that the inversion mode MOSFETs, fabricated by us in a 6 inch commercial foundry, have a lower ratio [R_on(150°C)/R_on(25°C)] than the accumulation mode MOSFETs, due to a better balance of change in channel and bulk mobility with temperature. Compared with typical commercially available MOSFETs, our fabricated accumulation mode and inversion mode MOSFETs exhibit a lower ratio [R_on(150°C)/R_on(25°C)], resulting in superior HF-FOM [R_onxQ_gd] at 150°C.

Abstract: Large-area, 7.84 mm² SiC DMOSFETs feature breakdown voltages of 4600 V, specific on-resistance of 17 mΩ-cm² and gate threshold voltage of 2.4 V. The low on-resistance was enabled by an optimized MOS process that resulted in channel mobility as high as 27 cm²/Vs, and oxide breakdown fields in the 10-11 MV/cm range. The key device design and layout parameters were varied to examine the performance versus reliability trade-offs.

Abstract: A comprehensive comparison of 3C-SiC and 4H-SiC power MOSFETs was performed, aimed at quantifying and comparing the devices’ on-resistance and switching loss. To this end, the relevant material parameters were collected using experimental data where available, or those obtained by simulation. This includes the bulk mobility as a function of doping density, the breakdown field as a function of doping and the MOSFET channel mobility. A device model was constructed and then used to calculate the on-resistance and breakdown voltage of a properly scaled device as a function of the doping density of the blocking layer. A SPICE model was constructed to explore the switching transients and switching losses. The simulations indicate that, for the chosen material parameters, a 600 V 3C-SiC MOSFET has an on-resistance, which is less than half that of a 4H-SiC MOSFET as are the switching losses in the device.

Abstract: Temperature-dependent mechanisms and characteristics of 4H-SiC JBS rectifiers were described by theoretical and experimental results. The forward on-resistance of 4H-SiC JBS rectifier consists of several components, the drift region resistance is most sensitive to temperature than others. Comparing theoretical results with experimental data indicates that the leakage current is mainly affected by the thermionic emission, the image force barrier height lowering and tunneling. At different temperatures and reverse bias, the contribution of barrier lowering and the tunneling to leakage current is not the same. The temperature of critical point decreases with the increasing of the concentration of N_D or the reverse bias voltage V_R. Samples with the doping concentration of N_D=6.5E15cm^-3 and N_D=1E16cm^-3 were manufactured in the same process. The forward I–V-T and reverse I–V-T characteristics of the JBS samples were measured at different temperatures (300K to 523K), and temperature-dependent ideality factor, barrier height and resistance were also analyzed, which are in good agreement with simulation results.

Abstract: The effect of a gate trench bottom p⁺ region (BPR) on the dynamic characteristics of 4H-SiC double-trench MOSFETs was investigated. Although employing a BPR led to an improved trade-off in the static characteristics, a BPR adversely affected the switching characteristics in spite of a reduction in the Miller capacitance compared to the case without a BPR_. Simulation analysis revealed that a resistance between a BPR and a source electrode led to an increase in the switching loss. We have found reduction of the resistance is insufficient in order to provide benefits from the BPR. Hence, it is necessary to improve layouts of contacts of the BPR to the source electrode.