Papers by Keyword: Post-Oxidation Annealing

Abstract: Single Event Gate Rupture (SEGR) is one of the catastrophic failures caused by heavy ions in power MOS devices. In this study, n-type SiC MOS capacitors representing the gate structure generally used in SiC power MOSFETs were used to conduct heavy ion irradiation tests to clarify the SEGR mechanism. The Linear Energy Transfer (LET) dependence of the critical electric field (E_cr) for these capacitors was evaluated with two different oxidation processes in accumulation to confirm whether the oxidation process affects SEGR tolerance. We found that the E_cr value and slopes of the LET dependence for SEGR between DRY samples and DRY + POA samples were approximately consistent. We also simulated SEGR and studied its mechanism. The simulation results suggested that SEGR for SiC MOS capacitors is caused by carriers in electron-hole pairs generated by a heavy ion instead of gate electric field fluctuation.

Abstract: Thermal oxidation of 4H-SiC to grow native-oxide SiO₂ is always followed by the generation of crystal defects and lattice distortion. We studied the relaxation of this distorted lattice on thermally-oxidized 4H-SiC surface by performing annealing process with several conditions. The surface distortion could be relaxed partially by annealing under argon, nitrogen monoxide, and H₂O gases, confirmed by in-plane X-ray diffractometer. This surface relaxation is possibly induced by the release of oxygen-related defects, as confirmed by thermal desorption analysis. The surface distortion caused by thermal oxidation is due to the existence of oxygen in 4H-SiC lattice, while the relaxation is caused by the migration of the oxygen-related defect structure, and emitted from 4H-SiC surface region as CO molecule.

Abstract: In this work, the interface between 4H-SiC and thermally grown SiO₂ is studied using low energy muon spin rotation (LE-μSR) spectroscopy. Samples oxidized at 1300 °C were annealed in NO or Ar ambience and the effect of the ambience and the annealing temperature on the near interface region is studied in a depth resolved manner. NO-annealing is expected to passivate the defects, resulting in reduction of interface traps, which is confirmed by electrical characterization. Introduction of N during annealing, to the SiC matrix, results in a thin, carrier rich region close to the interface leading to an increase in the diamagnetic asymmetry. Annealing in an inert environment (Ar) seems to have much lesser impact on the electrical signal, however the μSR shows a reduced paramagnetic asymmetry, indicating a narrow region of low mobility at the interface.

Abstract: The effect of the n-type 4H-SiC (0001) oxidation in wet O2 at temperature of 1175 °C followed by low temperature annealing in N2O at temperature of 800°C for 2 or 4 hours followed by high temperature annealing in nitrogen ambient on nitrogen distribution in silicon dioxide was investigated. It was shown that the oxidation and annealing have a strong impact on the behavior of electrical parameters of MOS capacitors using the oxides as gate dielectric what is probably an effect of nitrogen incorporation. The explanation of the observed electrical properties is included.

Abstract: In the present study, applying Al₂O₃ capping layer as suppressing layer of oxygen diffusion to SiC-MOS structures, we investigated the effect of Al₂O₃ layer as suppression of reoxidation at SiO₂/SiC interface and decrease of Dit. We evaluated MOS capacitors which have SiO₂/SiC and Al₂O₃/SiO₂/SiC structure on 4H-SiC (0001) Si-face epitaxial wafers after post-oxidation anneal process (N₂O:N₂=1:9 [slm]) at temperatures ranging from 1000 °C to 1300 °C for 30min. The Al₂O₃/SiO₂/SiC structure of reoxidation thickness, surface roughness and Dit are smaller than those of SiO₂/SiC structure. These results show that the suppression of reoxidation during POA is important to improve the SiO₂/SiC interfacial qualities.

Abstract: We investigated the effects of the post-oxidation annealing (POA) atmosphere on the electrical properties and interfacial roughness of SiO₂ deposited on a 4H-SiC (0001) face and SiC. POA in ammonia (NH₃) gave MOS capacitors with a lower interface trap density and n-channel MOSFETs with higher field-effect mobility than POA in nitrous oxide (N₂O) or nitrogen (N₂). In contrast, POA in N₂O gave a lower interface trap density than POA in N₂, but it gave the lowest field-effect mobility of all the samples. Cross-sectional TEM observations revealed that N₂O POA gave a higher interfacial roughness than NH₃ POA. We thus considered that N₂O POA degraded the inversion-layer mobility due to increased roughness scattering.

Abstract: In this work the field effect mobility measured on lateral n-channel MOSFETs in 4H-SiC with Al implanted body was correlated with the interface trap density measured on MOS capacitors. The test devices were fabricated on samples subjected to different post implantation annealing conditions (i.e. with or without a protective carbon capping layer) and to an identical post-oxidation annealing in N₂O. Despite the improved interfacial morphology, a reduction of the peak mobility (from 40 to 24 cm²V^-1s^-1) was observed using the carbon capping layer. An increase in the density of interface traps was consistently found. Nanoscale measurements of the active dopant concentration in the SiC channel region by cross-sectional scanning capacitance microscopy showed an higher compensation of p-type SiC for the sample processed without the capping layer, which indicates a more efficient incorporation of nitrogen at the SiO₂/SiC interface.

Abstract: We investigated the effect of post-oxidation annealing in wet O₂ and N₂O ambient, following dry O₂ oxidation on the SiC MOS interfacial properties by using p-type MOS capacitors. The interfacial properties were dramatically improved by the introduction of hydrogen or nitrogen atoms into the SiO₂/SiC interface, in each POA process. Notably, the N₂O-POA process at 1200 °C or higher reduced the interface state density more effectively than the wet-O₂-POA process, and offers a promising method to further improve the inversion channel mobility of p-channel SiC MOS devices.

Abstract: The electrical properties of oxides fabricated on n-type 3C-SiC (001) using wet oxidation and an advanced oxidation process combining SiO2 deposition with rapid post oxidation steps have been compared. Two alternative SiO2 deposition techniques have been studied: the plasma enhanced chemical vapor deposition (PECVD) and the low pressure chemical vapor deposition (LPCVD). The post-oxidized PECVD oxide is been demonstrated to be beneficial in terms of interface traps density and reliability.

Abstract: The effect of ammonia (NH3) post-oxidation annealing (POA) technique on the reliability of thermal oxides grown on a n-type 4H-SiC (0001) face by dry oxidation has been investigated. Comparing other POA techniques using hydrogen and nitrous oxide gases, it was indicated that the NH3 POA after dry oxidation remarkably improves the insulating properties of thermal oxides. The mode value of field-to-breakdown for thermal oxides prepared by NH3 POA was 12.1 MV/cm. The charge-to-breakdown (QBD) in the NH3 POA sample was the highest in all samples, and the QBD value at 63% cumulative failure rate was 19.1 C/cm2. In addition, the NH3 POA maintained excellent electron trapping characteristics of thermal oxides against the electron injection.