Papers by Keyword: Power Device

Abstract: In this work, 4H-SiC p-i-n diodes with excellent single-pulse avalanche energy density (EAS) with positively beveled mesa termination have been demonstrated. The fabrication of this junction termination extension (JTE) obviates ion implantation and requires only etching process. With its uniform electric field and temperature distribution, the fabricated 4H-SiC p-i-n diodes show breakdown voltage (BV) of 886V (98.4% of the parallel-plane limit) and the inductive avalanche energy density of ~10.4J/cm²@1mH. Meanwhile, ruggedness of the avalanche breakdown has also been evidently promoted. The results confirm that this structure exhibits great capability potential in power applications.

Abstract: In this paper we report the progress of our SiC trench etch development using enhanced ICP-based etch technology. Computer modelling of the electric field strength in the gate oxide as a function of corner geometry was used to illustrate trench corner rounding as an effective method to avoid to high gate oxide field strengths. This is an effort to examine a major ongoing issue in device reliability, and to govern future device design.

Abstract: Laser annealing process for ohmic contact formation on 4H-SiC has attracted increasing attention in the last years, because it enables the fabrication of SiC power devices on very thin substrates. We have investigated the formation of Nickel-based ohmic contact on 4H-SiC by using a Yb:YAG laser in scanning mode, with a wavelength of 515 nm and a pulse duration of 1200 ns. A 100 nm thick Ni layer has been deposited on SiC and irradiated at different process conditions. The reaction process has been studied, as a function of fluence and scan number of laser annealing, by means of X-Ray Diffraction (XRD) and Transmission Electron Microscopy (TEM) analyses. The electrical properties of the annealed layers have been evaluated on Schottky Barrier Diodes (SBDs) devices, confirming the ohmic behavior of the reacted contact and showing improved performances respect to RTA approach. The compatibility of thermal budget of the process in the front side has been verified by means process simulation. A strong relationship between structural properties of reacted layers and electrical behavior of SBDs devices has been revealed. Solid-state laser annealing process, with wavelength in green light region, can indeed represent a suitable solution for ohmic contact formation of 4H-SiC power devices, fabricated on thin substrates.

Abstract: In order to selectively analyze active thin layers close to surface in power devices structures, Raman scattering is necessary with UV excitation. However, the Raman spectra of GaN are usually affected by the direct bandgap photoluminescence of the material, which interferes with the Raman measurements and decreases the quality and resolution of the Raman spectra. In this work, we demonstrate experimentally that nanostructured aluminum films deposed on GaN epitaxial layers decrease the influence of the photoluminescence on the resonant Raman spectra and increase its overall spatial resolution under UV illumination.

Abstract: The commercial success of silicon carbide (SiC) diodes and MOSFETs for the automotive industry has led many in the field to begin developing ultra-high voltage (UHV) SiC insulated gate bipolar transistors (IGBTs), rated from 6 kV to 30 kV, for future grid conversion applications. Despite this early interest, there has been little work conducted on the optimal layout for the SiC IGBT, most early work seeking to overcome difficulties in fabricating the devices without a P+ substrate. In this paper, numerical TCAD simulations are used to examine the link between the carrier lifetime of SiC IGBTs and their short circuit capability. For the planar devices, simulations show that increasing carrier lifetime from 1 to 10 μs, has not only a profound effect reducing on-state losses, but also increases short circuit withstand time (SCWT) by 39%. Two retrograde p-well designs are also investigated, the optimal device for SCWT having a 100 nm channel region of 5×10¹⁶ cm^-3, with this increasing to a peak value of 2×10¹⁸ cm^-3, in a 700 nm region beneath the channel.

Abstract: PowerAmerica sponsored the development by NCSU of a process for manufacturing power MOSFETs and JBS Rectifiers in 2015. This process, named PRESiCE^TM, was successful in making 1.2 kV rated state-of-the-art 4H-SiC power devices (MOSFETs, BiDFETs, and JBS Rectifiers) in the X-Fab foundry. In addition, we were successful in monolithically integrating a JBS fly-back rectifier into the power MOSFET structure to create the power JBSFET which allows saving significant (~ 40 %) chip area and reducing package count in half. In the second year (2016), NCSU has qualified the process for manufacturing these power devices at X-Fab.

Abstract: In the ideal case, superjunction (SJ) drift regions theoretically exhibit a linear relationship between specific-on resistance R_on,sp and blocking voltage V_BR, but this requires perfect charge balance between the alternating n and p pillars. If any degree of imbalance exists, the relationship becomes quadratic, similar to a conventional drift region, although with somewhat improved performance. In this work, we analyze superjunction drift regions in 4H-SiC under realistic degrees of charge imbalance and show that, with proper design, a reduction in specific on-resistance of 2~10x is possible as long as the imbalance remains less than ±20%.

Abstract: The cubic polytype of SiC (3C-SiC) is the only one that can be grown on silicon substrate with the thickness required for targeted applications. Possibility to grow such layers has remained for a long period a real advantage in terms of scalability. Even the relatively narrow band-gap of 3C-SiC (2.3eV), which is often regarded as detrimental in comparison with other polytypes, can in fact be an advantage. However, the crystalline quality of 3C-SiC on silicon has to be improved in order to benefit from the intrinsic 3C-SiC properties. In this project new approaches for the reduction of defects will be used and new compliance substrates that can help to reduce the stress and the defect density at the same time will be explored. Numerical simulations will be applied to optimize growth conditions and reduce stress in the material. The structure of the final devices will be simulated using the appropriated numerical tools where new numerical model will be introduced to take into account the properties of the new material. Thanks to these simulations tools and the new material with low defect density, several devices that can work at high power and with low power consumption will be realized within the project.

Abstract: A high-temperature silicon carbide power module using CMOS gate drive technology and discrete power devices is presented. The power module was aged at 200V and 300 °C for 3,000 hours in a long-term reliability test. After the initial increase, the variation in the rise time of the module is 27% (49.63ns@1,000h compared to 63.1ns@3,000h), whilst the fall time increases by 54.3% (62.92ns@1,000h compared to 97.1ns@3,000h). The unique assembly enables the integrated circuits of CMOS logic with passive circuit elements capable of operation at temperatures of 300°C and beyond.

Abstract: Recently, sintering joint using Ag-nanohas been attracting attention as a new joint method to replace the solder. However, the joint layer would contain a lot of voids after sintering processes. Since the voids affect mechanical property, the proper sintering conditions have to be selected in order to reduce these voids. In this research, the authors focus on the effect of pressure conditions at sintering process. Then, by creating FEM models including voids from cross section image of the joint layer and carrying out tensile analysis, the mechanical property of the joint layer has been acquired. Using this approach, the influence of pressure conditions on the mechanical properties is revealed.