Papers by Keyword: Power Electronics

Abstract: The next space missions require power levels that current space qualified semiconductor technology cannot provide. The silicon carbide devices are considered to overcome these challenges, and provide the required technical performance. European space industry is asked in individual meetings about their specific needs and requirements, this information is gathered, classified and presented to the silicon carbide manufacturers. This work is the connection between the two industries to better understand the requirements and applications, and build a new business case for the SiC devices in space applications.

Abstract: In this work a groundbreaking SiC power MOSFET based on innovative vertical Gate All Around (GAA) concept is presented. Extensive TCAD simulations are performed to analyze the performance in forward as well as in reverse conditions for this new device concept. The proposed design has a target rating voltage of 1200V, suitable for e-mobility applications.

Abstract: In the recent past, lots of efforts have been put into further developing SiC power MOSFETs. In addition to optimization of device geometry, i.e., vertical device structure, various post-oxidation anneals have been studied to improve carrier mobility by reducing trap density. Nevertheless, a considerable number of traps remain, which are the central origin for dynamic changes in the threshold voltage of up to several volts during DC and AC operation. To explain the threshold voltage instability, an effective two-state defect model has been recently applied. In this work, we give an overview of modeling efforts to explain the impact of defects on the device threshold voltage and discuss the hysteresis of voltage sweep and bias temperature instabilities in SiC transistors. Based on the combination of measurements and computer simulations, a list of potential defect candidates responsible for the observed threshold voltage instabilities is discussed.

Abstract: Synchrotron X-ray topography techniques are used to characterize the microstructures in gallium nitride materials being developed for selective area doping for power electronic applications. Bulk substrates grown by different methods, epitaxial layers that are subject to ion implantation, annealing, etching and regrowth are characterized by X-ray topography in grazing incidence geometry and X-ray rocking curve topography. Strain and tilt maps of ion implanted epitaxial layers and etched and regrown wafers are generated. From the X-ray topographs, it is concluded that ammonothermal grown substrates show the highest quality among other types and most suitable for high-end electronic applications. It is also revealed that epitaxial growth, ion implantation and the annealing process do not change the dislocation distribution, but ion implantation introduces damage, strain and lattice bending effect, which are removed after annealing. Inductively coupled plasma (ICP) etching gives rise to strain variations in the wafer, while using tertiary butyl chloride (TBCl) to etch the wafer does not affect the strain distribution and can remove some damage from a preceding ICP etching process.

Abstract: With the growth in wide bandgap (WBG) semiconductors, specifically Silicon Carbide (SiC), the technology has matured enough to highlight a need to understand the drivers of manufacturing cost, regional manufacturing costs, and plant location decisions. Further, ongoing research and investment, necessitates analytical analysis to help inform development of wide bandgap technologies. The paper explores the anticipated device, module, and motor drive cost at volume manufacturing. It additional outlines the current regional contributors to the supply chain and proposes how the base models can be used to evaluate the cost reduction potential of proposed research advances.

Abstract: Continuous optimization of bulk 4H SiC PVT crystal growth processes has yielded an improvement in 150 mm wafer shape, as well as a marked reduction in stacking fault density. Mean wafer bow and warp decreased by 26% and 14%, respectively, while stacking faults were nearly eliminated from wafers produced using the refined process. These quality enhancements corresponded to an adjustment to key thermal parameters predicted to control intrinsic crystal stresses, and a reduction in crystal dome curvature.

Abstract: A novel solder bonding material for high-temperature applications based on Cu@Sn core-shell structured particles was developed, and the fabricated Cu@Sn particles were compressed into preforms for die attachment. The reflow temperature for this bonding material could reached as low as 260°C due to the low melting temperature of the outer Sn layer. However, after reflow soldering, the resulting interconnections can withstand a high temperature of at least 415°C, outer Sn layer completely transformed into Cu-Sn intermetallic compounds (IMCs) with high remelting temperatures. The formed bondlines exhibit good electrical conductivity due to the low porosity and the embedded Cu particles in the interconnections. Furthermore, the interconnections also exhibit excellent reliability under thermal shock cycling from-55°C to 200°C. This die attach material is suitable for power devices operating under high temperatures or other harsh environments.

Abstract: In this paper we report TDDB results on SiO₂/SiC MOS capacitors fabricated in a matured production environment. A key feature is the absence of early failure out of over 600 capacitors tested. The observed field accelerations and activation energies are higher than what is reported on SiO₂/Si of similar oxide thickness. The great improvement in oxide reliability and the deviation from typical SiO₂/SiC observations are explained by the quality of the oxide in this study.

Abstract: Efforts to develop 150 mm 4H SiC bare wafer and epitaxial substrates for power electronic device applications have resulted in quality improvements, such that key metrics match or outperform 100 mm substrates. Total dislocation densities and threading screw dislocation densities measured for 150 mm wafers were ~4100 cm^-2 and ~100 cm^-2, respectively, compared with values of ~5900 cm^-2 and ~300 cm^-2 measured for 100 mm wafers. While median basal plane dislocation counts in 150 mm samples exceed those of the smaller platform, a nearly 45% reduction was realized, resulting in a median density of ~3900 cm^-2. Epilayers grown on 150 mm substrates likewise exhibit quality metrics that are comparable to 100 mm samples, with median thickness and doping sigma/mean values of 1.1% and 4.4%, respectively.

Abstract: This article is an overview of research in fault diagnosis, detection, and reconfiguration. The review particularly focuses on power electronic applications and drives. Diagnostics of systems with conventional inverter drives (CID) is considered because knowledge of fault diagnosis in CIDs can be used for application in other inverter drive topologies; therefore, several techniques of fault diagnosis and reconfiguration in CIDs are analyzed.