Papers by Keyword: Power MOSFET

Abstract: We have demonstrated an integrated 3.3 kV 4H-SiC vertical planar bidirectional (BD) conventional (Conv) power DMOSFET in common-drain (CD) configuration using two commercially available power DMOSFET dies and study its operation down to 77 K (-196 °C) to evaluate its cryogenic static and switching performance. The BD conduction and blocking are achieved down to 77 K. The measured specific on-resistance (R_ON,sp) of the BD MOSFET at room temperature (RT) is 26 mΩ-cm², approximately twice that of the unidirectional device. It increases by 54% when cooled to 77 K due to a substantial increase in channel and possibly JFET on-resistance components. In addition, the extracted specific switching losses (E_ON,sp and E_OFF,sp) increases by 33% (13%) at 195K (–77 °C) and by 83% (88%) at 77 K, relative to their RT values. These increases are primarily attributed to the substantial rise in R_ON,sp at 77 K. As a result, the implemented BD Conv DMOSFET exhibits degradation in both on-state and switching performance under cryogenic operation, driven mainly by the significant increase in channel and JFET resistance components.

Abstract: Wide-bandgap silicon carbide (SiC) devices have shown great promise in power control systems due to its high efficiency and thermal stability. However, the absence of predictive compact models for SiC MOSFETs has hindered the validation of these benefits in power electronics applications through circuit simulations. To address this challenge, we introduce a physics-based SPICE model (PbSM) for SiC vertical power MOSFETs. This model is composed of basic subcircuit components that represent various regions in the MOSFET structure, which are physically modeled using a technology computer-aided design (TCAD) tool. By incorporating parasitic resistors into the PbSM, we incorporate the body effect within the MOS channel model with four terminals, thereby enhancing the capability of SPICE simulations. We include theoretical output (C_oss) and reverse transfer capacitances (C_rss) to simulate transient simulations based on a double-pulse test (DPT) setup. SPICE simulation results for static and dynamic characteristics have excellent agreement with the measured characteristics of a SiC MOSFET device, confirming the capability of the model in switching characteristics with voltage distribution across the multiple components. The PbSM shows the impact of parameter variations in switching performance, which promises valuable insights for modeling of the corner cases. Finally, the PbSM is computationally efficient, showing meaningful competitiveness compared to existing SPICE models for SiC power MOSFETs.

Abstract: Due to the expansion of defects like single Shockley-type Stacking Faults inside the SiC epitaxial drift layer, during high current stress, classical SiC MOSFETs can be victims of the degradation of their electrical characteristics. The introduction of an epitaxial SiC buffer layer between the substrate and the n- drift epilayer, called recombination-enhancing buffer layer, was shown to avoid this degradation. In this paper, TCAD simulations of the electrical behavior of such a commercial SiC MOSFET device with varying buffer layer thickness are studied, indicating only small modifications of the electrical characteristics. These simulations are combined with the characterization of the local electrical properties using an AFM-sMIM technique, allowing to determine the real thickness of the different layers of the device. These measurements highlight an inhomogeneous conductivity in the SiC substrate, being probably compensated by the introduction of the SiC buffer layer.

Abstract: In this study, a novel self-aligned process is proposed to reduce the specific channel resistance, and the electrical characteristics affected by process variation are also verified through TCAD simulation. Also, when compared to other self-aligned processes, the process introduced in this paper offers the advantages of stable electrical characteristics and lower process costs.

Abstract: In this work a reliability study of SiC power MOSFETs working as switching elements in a DC-DC Boost converter circuit is discussed. A critical parameter for a high-performance operation is the stable characteristics of the transistors employed. However, charge trapping effects such as bias temperature instabilities can affect e.g. the threshold voltage of transistors and thus lead to a variation in circuit behavior and efficiency. Furthermore, a time-dependent drift of the threshold voltage (ΔVth) of the MOSFET over time can cause an increase of the on-resistance (RDS(ON)) too, and thus affect the static on-state power losses accordingly (PON). In this work, we use our physical reliability simulator Comphy to extract the threshold voltage drift of the transistor over time for various mission profiles for gate biases under device operation. Using the extracted ΔVth values from the simulator, we can reproduce the measured behavior of the DC-DC boost converter circuit. With the calibrated toolset, we can obtain the ΔVth values over a long operation time to predict the aged behavior of the circuit parameters employing Spice simulations, which could be beneficial for circuit design and lifetime prediction of the system.

Abstract: SiC power MOSFETs show very promising electrical performance for efficient and reliable high temperature operation. This work presents a novel approach for the determination of the temperature dependence of SiC power MOSFET’s channel and drift resistance components in the on-state, which are extracted based on current-voltage (I-V) and capacitance-voltage (C-V) measurements without the need of data extrapolation. The results show that the channel resistance has weak, whereas the drift resistance has strong temperature dependence.

Abstract: This paper focuses on reporting the switching behaviour of our Silicon Carbide (SiC) power MOSFETs, rated 3.3kV – 25A. The devices are based on a gate stack formed by SiO₂/SiN and have been tested during Inductive Load Switching (ILS) in different conditions (nominal and SOA) with different chip configurations (single/multiple dies). In this contribution, the turn–on and turn–off curves are reported, along with the extracted RBSOA and switching energies.

Abstract: Dealing with electronic devices for high reliability applications in terrestrial environments, neutron-induced Single Event Effects must be investigated. In this paper, the experimental observation of an atmospheric-like neutron-induced Single Event Burnout (SEB) on a packaged commercial SiC power MOSFET is presented after irradiation at ISIS-ChipIr. The effects of the SEB in the electrical properties of the MOSFET are established, and the SiC damaged zone is observed by scanning electron microscopy. Based on this failure analysis at the die level, the distinct stages during the SEB mechanism can be defined. The sensitive volume where the secondary particle deposited enough energy to trigger the SEB mechanism is identified and located inside the SiC n-drift epitaxial layer near the epitaxial layer/substrate junction.

Abstract: We compare the failure mechanism and performance of a silicon carbide (SiC) semi-superjunction (semi-SJ) power DMOSFET against pure SJ and conventional DMOSFET when struck by a single heavy ion. The Single-Event Burnout (SEB) failure mechanism was identified as the thermal runaway from second breakdown resulting in mesoplasma formation. The semi-SJ design shifts the mesoplasma location from the drift/substrate interface seen in the control device structures to a location along the center of the P-pillar and closer towards the DMOSFET surface, thus significantly improving the SEB threshold voltage (V_SEB). The V_SEB varies with pillar width and ratio of pillar thickness to drift layer thickness. A maximum value of V_SEB is reached when the pillar to drift layer ratio is 0.9 and the pillar width is 2.4 μm. The semi-SJ SEB/breakdown voltage ratio is 100% and 13% higher than the pure SJ and conventional DMOSFET, respectively. Using a new Figure of Merit (FoM), which accounts for the tradeoff between V_SEB and on-state performance, we find that the SiC semi-SJ DMOSFET achieves a FoM that is 1.8 and 8 times higher than SJ and conventional DMOSFET, respectively, making the semi-SJ a competitive candidate for radiation hardened applications.

Abstract: This paper describes the mechanisms behind the failure of silicon carbide (SiC) Power MOSFETs (metal oxide semiconductor field effect transistors) when struck by a heavy ion. The modeled device is designed to simulate a commercially available 1200 V power MOSFET under the strike of a silver ion with a Linear Energy Transfer (LET) of 46 MeV-cm²/mg commonly used in single event effect (SEE) testing. The device is shown in simulation to fail near 500 V, which is in close agreement to experiments. The failure occurs near the interface between the epitaxial layer and the substrate layer due to the rapid increase of the electric field in that region and destruction of the device from impact ionization. Two improved designs were proposed and investigated that would help to mitigate the electric field in these regions and improve the device’s tolerance to single-event burnout (SEB). The new designs increased the voltage at which SEB occurs from 500 V to over 900 V and increased the specific on-resistance (R_on,sp) by only 5%.