Papers by Keyword: RIE

Abstract: Silicon Carbide is an exceptionally hard and challenging to process semiconductor material. Effective device singulation retaining 100% die yield is hard to achieve with conventional saw dicing. Chips, microcracks and machining abrasions lead to reduced die strength and increased scrap. With rapid advancements in SiC device processing, resolving many fabrication issues, dicing yield losses are becoming an area of industrial concern. Plasma dicing has a proven track record in silicon and presents a potential solution to low yields during SiC dicing. Smooth vertical sidewalls with no machining damage, with etch rates approaching 5 μm/min, position SiC plasma dicing as a viable alternative ready for industrial uptake. Plasma etch processes development using Ni and Cu etch masks, with full singulation have been demonstrated, resulting in improved die strength compared to saw diced samples.

Abstract: Effective control of device geometry is key to mitigating high localized electric fields in next-generation SiC power devices. Advanced trench processing allows for highly tunable trench-gate architectures in trench MOSFETs. By utilizing a two-step inductively coupled plasma reactive ion etch (ICP-RIE) process, a high degree of trench base corner rounding can be achieved, irrespective of trench opening corner geometry prior to post etch treatments. Sentaurus TCAD device modelling highlights the importance of effective electric field dispersion at the gate oxide using rounded trench corners, while I-V characterization of fabricated trench MOS-capacitor devices demonstrate the influence of trench base corner rounding on gate oxide breakdown.

Abstract: In this work, we examined the oxidation growth rates of the (0001) Si-face and (11−20) a-faces of 4H-SiC by carrying out oxidation in the 850°C-950 °C temperature range in a plasma afterglow furnace for application to trench MOSFETs. At 900 °C, this method results in almost equal oxide thickness on the Si-face and a-face which would nominally correspond to trench bottom and sidewalls in trench devices. Our results indicate that after NO annealing, the electronic properties of the plasma oxidized SiO₂/SiC interface is comparable to control samples with gate oxides formed by dry oxidation at 1150 °C followed by NO annealing. Next, the effect of reactive ion etching (RIE) of 4H-SiC surfaces prior to gate oxidation was investigated using planar 4H-SiC MOS capacitors. Our experiments show that oxidation followed by NO annealing of surfaces with smooth morphology following the RIE step, results in similar interface charge and trap densities as MOS capacitors which did not undergo the RIE etching.

Abstract: In this work, we present a planarization concept for epitaxial SiC trench structures involving reactive ion etching (RIE) and inductive coupled plasma (ICP) dry etching. The general idea is to transfer the flat surface from spun-on BCB/photo-resist layers to deposited silicon dioxide and finally to bulk SiC by applying process conditions with the same etch rate for the different materials. In this way several microns of unwanted material can be removed and planar SiC surfaces are obtained. With this method trench structures filled by epitaxial re-growth can be planarized with smooth surfaces and good homogeneity over the wafer. Cost-efficient device manufacturing can be achieved by using standard semiconductor process equipment. This technology makes it possible to manufacture advanced epitaxial SiC material structures for devices such as trench JBS diodes and double-gate trench JFETs.

Abstract: The important role of reactive ion etching (RIE) technique is to etch the semiconductor surface directionally. The purpose of the current research is to fabricate polysilicon micro-gap structures by RIE technique for future biosensing application. Therefore zero-gap microstructure of butterfly topology was designed by using AutoCAD software and finally the designed was transferred to commercial chrome glass photomask. Ploysilicon wafer samples were selected to achieve high conductivity during electrical characterization measurement. The fabrication process starts from samples resist coating and then by employing photolithography through chrome glass photomask the zero-gap pattern of butterfly topology was transferred to resist coated sample wafer followed by resist stripping from exposed area and finally by reactive ion etching (RIE) technique the open area of polysilicon was etched directionally at different etching time to fabricate micro-gap structure on wafer samples. The spacing of fabricated micro-gap structures will be further shrink by thermal oxidation (size reduction technique) until to nanosize gap spacing. The proposed nanospacing gap will definitely show the capability to detect the bio molecule when inserted into the gap spacing.

Abstract: Reactive Ion Etching (RIE) is an important process in fabrication of semiconductor devices. Design Of Experiment (DOE) has been used to study the effect of Reactive Ion Etch (RIE) towards surface morphology of aluminum bond pad. Important RIE factors involved in this experimental study are ratio of Tetrafluoromethane (CF₄), Argon gas flow, BIAS, and ICP power. Different combinations of these factors produces different results of surface morphologies which was obtained using Atomic Force Microscopic (AFM). Produced results shows that overall surface roughness of the pad is affected by RIE and DOE offers a better way to optimize the desired outcome.

Abstract: Design of Experiment (DOE) is a technique for optimizing process which has controllable inputs and measurable outputs. As a method of DOE, 2⁴ Full Factorial design is used to study the effect of Reactive Ion Etch towards the surface roughness of aluminum pad and effect of the roughness produced towards the contact angle. Surface roughness analysis is done using Atomic Force Microscop (AFM). Contact angle is measured using AutoCad software from the images captured from droplet test. This contact angles must be more than 90° for non-wetting profile or less than 90° for wetting profile. This work is also done to understand the interaction between the process parameters and how each parameters will affect the etch rate. The results are analyzed which shows that the increase in surface roughness produces an increase on the contact angle and vice versa.

Abstract: This study reports on the preliminary investigations on the effect of Reactive Ion Etch (RIE) parameters on the surface characteristics of Al bond pad. Investigation is done employing Design of Experiment (DOE) method. Quantity of Oxygen, Argon, ICP power and BIAS power were varied to get 16 sets of recipes. This provides 16 samples with different combination of RIE parameters. Surface characteristics of the samples were analyzed using Atomic Force Microscopy (AFM).Data collected were in terms of Surface Roughness (RA), Peak Vs Valley (P-V) and Surface Root-Mean-Square Roughness (RMS). Result shows that combination of these RIE parameters does not vastly affect the surface characteristics of the Al bond pad.

Abstract: Reactive Ion Etching (RIE) is an important process in fabrication of semiconductor devices. Design Of Experiment (DOE) has been used to study the effect of Reactive Ion Etch (RIE) towards surface morphology of aluminum bond pad. Important RIE factors involved in this experimental study are ratio of Tetrafluoromethane (CF₄), Argon gas flow, BIAS, and ICP power. Different combinations of these factors produces different results of surface morphologies which was obtained using Atomic Force Microscopic (AFM). Produced results shows that overall surface roughness of the pad is affected by RIE and DOE offers a better way to optimize the desired outcome.

Abstract: A high selectivity patterning technology of vanadium oxide (VO_x) thin film was suggested in this paper. VO_x thin film was etched through a photoresist (PR) mask using Cl/N based gases in a reactive ion etching (RIE) system. Taguchi method was used for process design to identify factors that influence the patterning and find optimum process parameters. Experimental results suggested that RF power was the largest contribution factor for VO_x etch rate, PR selectivity and uniformity on 6 inch diameter wafer. Uniformity and PR selectivity were improved by introducing a small amount of N₂. High resolution and low roughness patterning transfer was achieved with a non uniformity of 2.4 %, an VO_x etch rate of 74 nm/min, a PR selectivity of 0.96, a Si₃N₄ selectivity of 5 and a SiO₂ selectivity of 10.