Papers by Keyword: Reliability

Abstract: This study evaluates the performance and reliability of SiC n-and p-MOSFETs across a temperature range from room temperature up to 400°C, focusing on field effect (FE) mobility and threshold voltage variations under high thermal and bias stress conditions. By analyzing the variations in field effect mobility and threshold voltage under different stress conditions, our study illustrates distinct behaviors between devices with thermally grown oxides and those with chemical vapor deposited (CVD) oxide layers, underscoring significant differences in long term performance. Results indicate that while n-MOSFETs maintain threshold voltage shifts below 3% and exhibit robust characteristics up to 400°C, p-MOSFETs exhibit permanent threshold voltage shifts of up to 10% and mobility reductions of 15% particularly above 300°C DC stress. The 2 nm ultrathin thermal (UT) followed by 40nm CVD SiO₂, outperform thermal oxides, sustaining less degradation in mobility and less shift in threshold voltage under bias temperature instability (BTI) conditions at voltages up to ±25V and temperatures as high as 400°C. This research advances SiC CMOS technology by confirming that SiC n-MOSFETs are ready for high-temperature circuit applications, while highlighting the need for further improvement in p-MOSFETs to enhance their reliability under extreme conditions.

Abstract: In this work, we propose and experimentally validate a novel approach to achieve superior interface properties of the SiO₂/SiC MOS capacitors through a low-temperature oxide deposition technique for gate dielectric followed by a nitridation process. Low interface trap density (~ 5×10¹⁰ eV^-1cm^-2), robust flat-band voltage stability under positive bias stress, and decent leakage current density (J_G ~ 5×10^-10 A cm^-2) can be unambiguously verified after nitric oxide (NO) gas post-deposition annealing.

Abstract: Due to the lack of internationally accredited quality standards for silicon carbide (SiC) epiwafers, vendors provide defect maps using different metrology techniques and naming conventions, making it difficult to draw correlations between defect types and unclamped inductive switching (UIS) behavior. This study tested 1700 V rated Junction Barrier Schottky Diodes (JBS) using materials from five 4H-SiC epiwafer suppliers and concluded that, without maps having industry-standardized defect names and showing precise locations, sizes, and shapes, device manufacturers cannot effectively predict UIS yield and reliability.

Abstract: In this work, a comparison of standard bulk 4H-SiC epi wafers and Soitec's SmartSiC™ wafers as well as the influence of RTA processing was conducted. For this, MOS capacitors were processed using thermal gate oxide paired with a polycrystalline gate electrode. Subsequent High temperature steps were avoided until an RTA process was performed on some of these wafers. To investigate the oxide quality on all wafer and process splits, CV-, time-zero dielectric breakdown and constant-current stress time-dependent dielectric breakdown measurements were carried out. For the examination of bulk wafers and SmartSiC™, no relevant differences in terms of yield, oxide quality, interface state density and reliability were found. In contrast, RTA processes seem to create a shift in flat band voltage and also lead to a reduction in oxide lifetime. The V_FB shift could partially, but not completely, be explained by addition activation of dopants in the polysilicon electrode. The influence on the oxide reliability, however, is still unclear.

Abstract: The reliability of the distribution networks has been threatened by the disturbances which have occurred on the said networks and which have led to supply interruptions to customers. From the analysis of the faults that have occurred on these networks, it emerged that the most recurring disturbances are faults originating from external causes (atmospheric overvoltages, violent winds) and which represent 90% of the causes, transient faults (70%) and broken conductors (40%). The study of the reliability indices showed that the most disturbed departures are the MV departures from Ouidah, ITTA, Calavi and Togba whose SAIDIs are respectively 15.64; 13.9; 10.05; and 8.52. The optimization of the maintenance plan by genetic algorithms of the NSGA II type made it possible to identify the number of inspections which is 5 days and 11 days respectively during the rainy season and the dry season. The inter-inspection period related to these inspection periods is (21 days). This study led to the proposal of an optimal plan taking into account climatological criticalities and the aim of which is to reduce these disturbances which are more untimely in the rainy season. The resolution of the reliability problem by genetic algorithms of the NSGA-II type made it possible to deduce that the undistributed energies are reduced by 92.22% on the departure of Togba, 93.43% on the departure of ITTA and 95, 54% on departure from Ouidah. This energy could have brought Beninese Electricity Company (SBEE) a sum of nine hundred fifty-one million eighty-four thousand two hundred and fifty CFA francs (951,084,250 FCFA) on only three MV departures. This optimization denotes the technical and financial interest of SBEE by focusing more on strategies for reducing disruptions on its networks while giving priority to the rehabilitations, effectiveness and efficiency of its maintenance plans. The methodology used is efficient and effective and can allow SBEE to make substantial savings which will enable it to make a reinvestment in its distribution networks.

Abstract: The paper examines a complex methodology for calculating the slope stability of a tailing storage facility based on comparing the results obtained through deterministic and probabilistic approaches. The analysis is performed in GeoStudio software, based on the limit equilibrium method, and with a probabilistic approach that uses a Monte Carlo simulation to compute a probability distribution of the resulting factor of safety. A slope stability assessment of tailing dam was conducted on the example of Ferrexpo Poltava Mining, and a conclusion was reached about their reliability and safety. The results of the deterministic analysis showed that the calculated factor of safety is by those established in Ukrainian regulatory standards. It has been recognized that the factor of safety is not a consistent measure of risk for tailings dam. Considering the variability inherent in the soil materials of tailings dam is a way to achieve more accurate results. The importance of obtaining a failure probability and a reliability index due to tailing dam stability was highlighted by comparing deterministic and probabilistic approaches.

Abstract: The total ionising dose (TID) reliability of a phosphorous pentoxide (P₂O₅) treated SiO₂ (silicon dioxide) layer is compared for the first time to other industrially relevant oxides formed on 4H-silicon carbide (SiC). Metal-oxide-semiconductor capacitors (MOSCAPs) are characterised before and after irradiation to ascertain changes in flat band voltage shift, leakage current, and dielectric breakdown (BV). Secondary ion mass spectrometry (SIMS) profiling reveals a significant phosphorus concentration near the SiO₂/SiC interface, which led to improved TID resistance. The P₂O₅ treated oxide had the lowest leakage current at high voltage bias due to the high-temperature (1,000°C) anneal, though it had a significantly negative flat band voltage due to the high concentration of deposited phosphorus atoms. The thermal and P₂O₅ oxides demonstrated a TID resistance, suffering only minor shifts in flat band voltage, while the P₂O₅ oxide suffered the smallest decrease in its BV and the smallest leakage current rise, post-irradiation.

Abstract: In this study we analyzed the physical mechanisms governing time-dependent dielectric breakdown (TDDB) and we used TDDB physical model of dielectric breakdown, implemented in the defect-centric Ginestra® modeling platform, to deconvolute the intrinsic material properties effects and geometry feature impact on the gate oxide (GOx) and SiC-device breakdown.

Abstract: Dynamic on-state resistance has been experimentally observed in all commercially-available SiC MOSFETs studied on the time scale of normal device operation, and can be explained by the presence of dynamic threshold-voltage instability. The magnitude of this dynamic on-state resistance varies from vendor to vendor, but in every case this magnitude generally corresponds to the magnitude of that device’s threshold-voltage instability, as described by standard textbook equations-especially in the case of large threshold-voltage instabilities.

Abstract: In this paper, 1.2 kV SiC trench MOSFET with deep P structure has been proposed to effectively shield the trench bottom oxide. The various design splits, such as N concentration between deep P and deep P to trench distance, were experimentally evaluated and TCAD simulations were performed to extract maximum oxide electric field at trench bottom. Based on trade off results, critical design parameters were optimized to obtain low Rdson and stable breakdown voltage with acceptable oxide electric field. To evaluate trench gate oxide reliability in wafer level, gate oxide integrity (GOI/Vramp), charge to breakdown (QBD), and time dependent dielectric breakdown (TDDB) tests were conducted. Also, high temperature gate bias (HTGB) and high temperature reverse bias (HTRB) stress tests were carried out for assembled samples to compare device reliability depending on different designs. For the target design, the promising reliability results were confirmed in both wafer level and assembled samples.