Papers by Keyword: Reliability

Abstract: Cumulative heavy-ion irradiation effects were investigated in a commercial 4H-SiC double trench MOSFET through a combination of cyclotron experiments and TCAD simulations. Devices were exposed to continuous ¹²⁴Xe³⁵⁺ ion strikes at a linear energy transfer (LET) of 63 MeV·cm²/mg under drain biases from 100 to 400 V. Experimental results revealed the onset of permanent drain and gate leakage at voltages as low as 200 V, with degradation rates increasing by several orders of magnitude at higher bias. Post-irradiation measurements confirmed trench oxide rupture and source leakage path formation, establishing single-event leakage current (SELC) as the dominant degradation mechanism. In contrast, TCAD simulations of isolated ion strikes predicted catastrophic single-event burnout (SEB) only at or above 250–300 V, highlighting the critical role of cumulative damage processes that are not captured in single-strike models. These findings demonstrate that permanent leakage-driven degradation effectively extends the SELC zone beyond conventional SEB thresholds, reducing the safe operating area of trench-based SiC MOSFETs. The results have significant implications for derating strategies in space applications, where current SEB-focused guidelines may underestimate vulnerability, and highlight the need for radiation-hardening by device design to ensure long-term reliability.

Abstract: This study investigates the degradation behavior of 1200 V 4H-SiC planar MOSFETs under negative high-temperature gate bias (HTGB) stress. The devices were stressed at −20 V and 150 °C for 1008 hours. Key electrical parameters, including threshold voltage (V_th) and reverse transfer capacitance (C_rss), were monitored to evaluate time-dependent changes. The results reveal a clear two-phase degradation behavior characterized by a transition between electron-dominated and hole-dominated charge injection mechanisms. In the early stage, electron injection via Fowler–Nordheim (FN) tunneling causes a positive shift in V_th and a reduction in C_rss. With prolonged stress, partial charge compensation leads to a reversal of the electrical trends. These results demonstrate a time-dependent transition between electron injection and hole injection mechanisms. The findings provide insight into the long-term reliability of planar SiC MOSFETs under negative HTGB stress.

Abstract: As a switching device, a SiC MOSFET operates under high-frequency and fast switching edges, facing severe reliability challenges in the dynamic mode. The degradation of electrical characteristics of SiC MOSFETs under high-voltage dynamic switching conditions is systematically investigated in this study. It is found that the threshold voltage and on-resistance exhibit initial transient degradation but they both stabilize, with changes remaining within ±5%. They show no dependence on the pulse amplitude, frequency, duty cycle, or temperature. This is attributed to the shielding effect of the P-well structure on the electric field in the channel region, which suppresses the continuous accumulation of interface charges. Additionally, the body diode voltage drop shows no significant shift, indicating that the dynamic reverse bias stress has no substantial impact on the n-drift region. However, the blocking capability can degrade and the degradation trajectory exhibits cross-coupling effects of multiple factors. The rate of degradation is positively correlated with the pulse voltage amplitude, frequency, duty cycle, and test temperature. As these stressors increase, carriers gain higher energy in the couple electro-thermal fields, leading to enhanced charge injection efficiency and trapping depth, increased interface charge accumulation, and localized electric field distortion, resulting in nonlinear degradation of the device's blocking capability. This study reveals the degradation mechanisms of SiC MOSFET under dynamic stress conditions, providing a theoretical basis for the optimization of interface engineering and dynamic operation adaptation design of high-reliability power devices.

Abstract: The long-term reliability of silicon carbide MOSFETs is critically influenced by the stability of the gate oxide, which is susceptible to degradation due to high defect densities at the oxide-semiconductor interface. This work presents a comprehensive investigation of gate oxide degradation in next-generation SiC MOSFETs, comparing planar and trench device topologies under both static and dynamic stress conditions. Time-dependent dielectric breakdown measurements reveal degradation phases that are strongly dependent on device topology. Comparative analysis of various gate stress methodologies shows that dynamic switching stress exerts a more pronounced impact on trench devices than on planar devices. Thus, highlighting the need of tailoring reliability test protocols to the specific device topology, rather than adopting a generalized approach.

Abstract: In standard environmental reliability tests, Silicon Carbide (SiC) MOSFETs show a superior performance compared to their Silicon counterparts. This raises the question if the SiC modules are robust and reliable under all circumstances in the field and against all failure mechanisms or only in the standard laboratory tests. The HV-H³TRB (High Voltage – High Humidity High Temperature Reverse Bias) test is the standard test for humidity reliability and SiC modules survive this test for several thousand hours, easily surpassing the 1,000 h qualification requirement. However, in field service the devices are exposed to steep voltage slopes (high dv/dt) instead of the DC voltage stress applied in a standard HV-H³TRB. In this work, a dynamic HV-H³TRB test was performed on 3.3 kV SiC MOSFET modules for more than 4,000 h with switched high voltages of 80% V_nom, only observing minor degradations and reversible blocking capabilities.

Abstract: In this work, the power cycling capability of discrete SiC MOSFETs of seven manufacturers is investigated. The results show that even nominally similar devices can exhibit substantially different power cycling capabilities. The differences among the tested devices involve the scaling factor and the slope of the lifetime curves, but also the dependence of the baseline temperature. Furthermore, some devices exhibit a considerable increase in power cycling performance towards lower temperature swings, which cannot be characterized properly by power cycling tests at typical test conditions with much larger temperature swings. Thus for a proper assessment of the power cycling performance, multiple tests at suitable test conditions are necessary to obtain meaningful results.

Abstract: The pursuit of ever-higher system efficiency and power density in power electronic applications paves the way for an increased utilization of wide bandgap semiconductor devices such as silicon carbide (SiC) MOSFETs, due to reduced conduction and switching losses compared to silicon. For real-world application reliable operation along its lifetime is of utmost importance. To assure robust operation in electric drives and traction inverters SiC MOSFETs are switched bipolar to prevent parasitic turn on. Recently, it has been shown that not only bias temperature instability, but also gate-switching instability in bipolar switched applications has to be considered as a reliability concern for SiC MOSFET. While in gate switching stress tests usually only critically damped conditions are investigated irrespective of rise and fall times, in real-world applications gate voltage overshoots may occur and a broad variety of slew rates may be used depending on the individual power converter design. Therefore, this work investigates the influence of gate voltage overshoot and voltage slopes on threshold voltage aging using high frequencies and online degradation monitoring. It is shown that overshoots have a dominating impact on the overall degradation, while the gate voltage slope impacts minorly.

Abstract: This work determines the reliability indices of the Nigeria 330kV electric power network, which is susceptible to disturbances. Besides, the network configuration is inadequate as it is vulnerable, resulting in transmission line outages. The cardinal object, therefore, is to benchmark the indices against established standards to enable effective operational improvement planning. First, a simulation was conducted using the Electrical Transient Analyzer Program (ETAP) and validated with the Power System Simulator for Engineering (PSS/E) software to assess bus voltages, line flows, and system losses. Subsequently, the ETAP software was applied to determine reliability indices such as the System Average Interruption Frequency Index (SAIFI), System Average Interruption Duration Index (SAIDI), Customer Average Interruption Duration Index (CAIDI), Average Service Availability Index (ASAI), Average Energy Not Supplied (AENS) and Expected Energy Not Supplied (EENS). The simulation results obtained for SAIFI, SAIDI, CAIDI, and ASAI on the test network are 3.2684 f/customer. yr, 9.4140 hours per customer in a year, 2.880 hours per customer interruption, and 0.9989 respectively. Likewise, the AENS with gave a high value of 1360.9340 MWh/customer. yr indicating that on the average, customer is are expected to lose access to 1360.9340 MWh of energy annually. Furthermore, the high value of EENS estimated at 55,798.300 MWh/yr means that the power system is expected to fail to supply 55,798.300 MWh of electricity in one year due to various incidents of failure. These values were compared with the standard IEEE values and were found to be outside the threshold; thus, making it imperative that the indices be utilized to undertake further work that would result in improved and efficient operation of the national grid.

Abstract: The formation of high-quality ohmic contacts on the backside of thinned SiC wafers is critical for vertical power devices to minimize specific on-resistance and enhance energy efficiency. Conventional green laser (532 nm) annealing for Ni-based backside metallization faces challenges such as severe carbon out-diffusion, interfacial voids, and high contact resistivity. This work introduces a Ni/Ti composite metallization scheme combined with 355 nm ultraviolet laser annealing (UV-LA) to address these limitations. By replacing the Ni single-layer with a Ni/Ti stack layer, the reflectivity at 355 nm UV laser annealing is reduced, enabling efficient energy absorption and localized alloying. Ti acts as a diffusion barrier, suppressing Kirkendall void formation and immobilizing carbon through in-situ TiC formation, as confirmed by XRD analyses. Additionally, UV-LA at 4.2 J/cm² with Ni/Ti composite metallization optimizes reaction kinetics, achieving a 69% reduction in void density and a 65% improvement in alloy layer flatness compared to Ni alloy layer. The results validate Ni/Ti-UV-LA as a scalable solution for high-reliability SiC backside metallization, paving the way for next-generation power devices.

Abstract: This study evaluates the performance and reliability of SiC n-and p-MOSFETs across a temperature range from room temperature up to 400°C, focusing on field effect (FE) mobility and threshold voltage variations under high thermal and bias stress conditions. By analyzing the variations in field effect mobility and threshold voltage under different stress conditions, our study illustrates distinct behaviors between devices with thermally grown oxides and those with chemical vapor deposited (CVD) oxide layers, underscoring significant differences in long term performance. Results indicate that while n-MOSFETs maintain threshold voltage shifts below 3% and exhibit robust characteristics up to 400°C, p-MOSFETs exhibit permanent threshold voltage shifts of up to 10% and mobility reductions of 15% particularly above 300°C DC stress. The 2 nm ultrathin thermal (UT) followed by 40nm CVD SiO₂, outperform thermal oxides, sustaining less degradation in mobility and less shift in threshold voltage under bias temperature instability (BTI) conditions at voltages up to ±25V and temperatures as high as 400°C. This research advances SiC CMOS technology by confirming that SiC n-MOSFETs are ready for high-temperature circuit applications, while highlighting the need for further improvement in p-MOSFETs to enhance their reliability under extreme conditions.