Papers by Keyword: Reverse Recovery

Abstract: We report an anomalous reverse-recovery (RR) of the body diode in a 3.3 kV 4H-SiC superjunction (SJ) DMOSFET: at 77 K, Q_RR,sp increases by 1.4×–3.5× versus room temperature and 5× versus 195 K, and J_PR increases by >2×, while t_RR changes by only <30ns. A clear dependence of Q_RR,sp on the ramp rate at 77K indicates the Q_RR,sp is not due to additional depletion charge. Current-controlled negative resistance (CCNR) is also observed solely for the SJ body diode at 77K. The voltage waveforms strongly suggest the additional Q_RR,sp is due to dynamic breakdown of the SJ due to transient charge imbalance of the pillars caused by delayed hole emissions of the deep acceptors. The anomalous behavior is qualitatively reproduced in simulation. We also benchmark a 3.3kV Charge Balance (CB) 4H-SiC DMOSFET along with the SJ device from 77–423 K using an inductive double-pulse test. For T > 77 K the switching for both devices is dominated by the depletion capacitance (weak Q_RR,sp dependence on the ramp rate): the SJ device turns off faster (t_RR = 0.3–0.8× CB), is snappier (t_B/t_A = 0.23–0.56× CB), and shows larger J_PR (1.8–2.8× CB) while recovering less charge (Q_RR,sp = 0.4–0.8× CB). The CB device shows the expected increase of Q_RR,sp with temperature and only modest t_RR temperature variation. Overall, the CB device provides softer, predictable RR without a cryogenic anomaly, whereas SJ delivers the shortest t_RR above 77 K but exhibits the 77 K anomalous increase and is consistently snappier.

Abstract: We generalize a recent Si P-i-N reverse-recovery (RR) model to more accurately capture 4H-SiC diode behavior by adding deep-acceptor-limited anode injection, strong recombination (due to >100x shorter optimized high-level lifetimes compared to Si), and improved modeling of the depletion layer dynamics. Closed-form expressions for the growth of the depletion layer are derived, enabling analytical estimates for Q_RR, t_RR, and J_PR. The model is validated against Sentaurus RR simulations of optimized 4H-SiC P-i-N diodes spanning BV = 6–17kV and di/dt = 10 A/µs–10 kA/µs, achieving an average reduction in error of >90% for estimations of key switching performance parameters (Q_RR, t_RR, J_PR). By correctly capturing the dependence of Q_RR on di/dt, the model enables better estimates for the high-level lifetime (τ_HL) directly from the RR waveforms. The differential form enables straightforward utilization of the model to analyze non-idealized RR waveforms. Overall, the generalized model reveals a more favorable Q_RR–V_F trade-off than implied by the unmodified Si model and improves first-order device optimization prior to full design.

Abstract: This study investigates static and dynamic behavior of a 3.3 kV semi-Superjunction (SJ) MOSFET, compared with a conventional planar MOSFET. The semi-SJ was designed using a cost-effective trench side-wall implantation and SiO₂ refill fabrication method and evaluated through TCAD simulations. The optimized semi-SJ MOSFET designs, reduces R_ON by 19% and increases BV by 500 V compared with the planar MOSFET, while maintaining a comparable reverse recovery charge (Q_RR). The proposed semi-SJ design demonstrated the best R_ON×Q_RR figure of merit (17.8 mΩ·µC), outperforming the conventional planar MOSFET design (19.7 mΩ·µC).

Abstract: MeV-SJ-MOSFET with short tapered SJ columns was developed by high-energy (MeV) Al ion implantation and was evaluated for the reverse recovery characteristics and the body diode reliability compared to those of Multiepi-SJ. MeV-SJ alleviated the increase in on-resistance at elevated temperatures regardless of short SJ columns and exhibited soft reverse recovery characteristics due to the short tapered SJ shape. MeV-SJ also suppressed the body diode degradation more than Multiepi-SJ. It was considered that the carrier lifetime of drift layer of MeV-SJ may be decreased by non-radiative defects.

Abstract: We have introduced a new 1200V 4H-SiC MOSFET as Wolfspeed's Gen4 MOSFET, which offers compatible Rds,on, improved dynamic switching energy losses, reduced Qrr, and enhanced short circuit withstand time performance. In this study, we examine the P-body effect resulting from multi-step ion implantation and its significant impact on both the static and dynamic characteristics of SiC MOSFETs, specifically focusing on body-diode reverse recovery, short circuit withstand time (Tscwt), and observed switching energy losses in the 1.2 kV 4H-SiC power MOSFETs within this Gen4 series. Our findings are expected to contribute valuable insights into optimizing the design and operation of SiC MOSFETs, ultimately supporting the needs of modern power electronic systems that demand greater performance and efficiency.

Abstract: The improvement of the electrical properties of power semiconductors using engineered substrates is becoming increasingly significant. This paper investigates the dynamic performance and robustness of SiC MOSFETs based on SmartSiC^TM engineered substrates, focusing on the reverse recovery of the body diode and their ruggedness under overload conditions such as short-circuit and surge current. A comparison with SiC MOSFETs based on conventional monocrystalline substrates was performed to evaluate the results. A significant decrease in reverse recovery charge was observed, particularly at higher temperatures, while the robustness during short-circuit type I and surge current was not affected.

Abstract: In this paper, Shockley-Read-Hall (SRH) lifetime depth profiles in the drift layer of 10 kV SiC PiN diodes are calculated after MeV proton implantation. It is assumed that the carbon vacancy will be the domination trap for charge carrier recombination and the SRH lifetime is calculated with defect parameters from the literature and proton-induced defect distributions deduced from SRIM calculations. The lifetime profiles are imported to Sentaurus TCAD and static and dynamic simulations using tailored lifetime profiles are carried out to study the electrical effect of proton implantation parameters. The results are compared to measurements, specializing on optimization of the trade off between on-state and turn-off losses, represented by the forward voltage drop, V_T, and reverse recovery charge, Q_rr, respectively. Both the simulated and measured IV characteristics show that increasing proton dose, or energy, has the effect on increasing forward voltage drop and on-state losses, while simultaneously, the localized SRH lifetime drop decreases the plasma level, increases the speed of recombination and decreases reverse recovery charge. Finally, TCAD simulations with different combinations of proton energies and fluences are used to optimize the trade-off between static and dynamic performances. Reverse recovery charge and forward voltage drops of these groups of diodes are plotted together, showing that a medium energy which induces the most defects in the depletion region relatively close to the anode gives the best dynamic performances, with a minimum cost of static performance.

Abstract: In this paper, proton implantation with different combinations of MeV energies and doses from 2×10⁹ to 1×10¹¹ cm^-2 is used to create defects in the drift region of 10 kV 4H-SiC PiN diodes to obtain a localized drop in the SRH lifetime. On-state and reverse recovery behaviors are measured to observe how MeV proton implantation influences these devices and values of reverse recovery charge Q_rr are extracted. These measurements are carried out under different temperatures, showing that the reverse recovery behavior is sensitive to temperature due to the activation of incompletely ionized p-type acceptors. The results also show that increasing proton implantation energies and fluencies can have a strong effect on diodes and cause lower Q_rr and switching losses, but also higher on-state voltage drop and forward conduction losses. The trade-off between static and dynamic performance is evaluated using Q_rr and forward voltage drop. Higher fluencies, or energies, help to improve the turn-off performance, but at a cost of the static performance.

Abstract: Substituting Si diodes with SiC Schottky diodes in Si insulated gate bipolar transistor (IGBT) modules is beneficial, as it can reduce power losses in electrical systems significantly. The fast switching nature of the SiC diode will allow Si IGBTs to operate at their full high-switching-speed potential, which at present is not possible because of the Si diodes. In this work, the electrical test results for Si-IGBT/4HSiC-Schottky hybrid substrates (hybrid SiC substrates) are presented. Comparisons of the 6.5 kV Si and hybrid SiC at room temperature and high temperature have shown that the switching losses in hybrid SiC substrates are low as compared to those in Si substrates but necessary steps are required to mitigate the ringing observed in the output waveforms.

Abstract: The nature of diode reverse recovery is analyzed in this paper, and the reverse recovery loss is evaluated in a BOOST PFC converter using a silicon (Si) or silicon carbide (SiC) diode in the forward branch. Mathematical models of the forward conduction and reverse recovery losses are established to assess the influence of Si and SiC diodes. To characterize and quantify the losses related to diode reverse recovery, an 85~265V AC to 400V DC, 2kW BOOST PFC prototype is built with switching frequencies of 65kHz. It is found that the reverse-recovery inherent in a Si diode cannot be neglected. The switching loss is substantially smaller when the diode is a SiC one. In order to investigate further, a double pulse test rig is established, with the switch and the diode being either Si or SiC. The experimental results demonstrate that with a SiC diode, not only the diode conduction losses but also the transistor turn-on loss is greatly reduced.