Papers by Keyword: SOPC

Abstract: This paper analyzed the principle of the two-dimensional FFT algorithm, and adopted the time domain extracted base 2D-FFT algorithm and CORDIC to achieve a one-dimensional FFT IP core in Quartus II platform, then used this IP core matrix transposition module to structure 2D-FFT core processing unit desired. In SOPC system, we adopted custom components and IP core packaging technology and adding the integration of the module. Completed the design of SOPC system, which was simulated and downloaded to the development board for verification and the test results were compared to the Matlab operation results. The simulation and test results showed that this design had a simple hardware structure, high throughput, high stability and a good prospect.

Abstract: The paper uses soft nuclear CPU as controller created by SOPC, Combins with Ethernet controller components to realize the collection and transmission of multiple rate data.Discusses the characteristic parameterss affect to the CIC and hb filter, and has a optimal design: Demonstrates the best value range of CIC filters order number and extraction ratio, then compensates for bandpass characteristics; hb filter adopts multiphase structure which can improve efficiency.

Abstract: Along with the development of advanced control system, in order to achieve the goal of low energy consumption, low pollution and high degree of automation, the coordination matching work of the motor driving electric motor car and the car body has a better future. By using GW48 hardware development platform and the SOPC technology of nuclear NiosII in FPGA as the central processing unit, and with the aid of the Avalon the peripheral circuit of the motor driving electric motor car is completely under control. This is a improvement of the classic control of the motor (i.e. based on single chip or DSP motor control). This article introduces the design method of the drive control system for electric motor cars. A function module design is conducted for the hardware part, which includes the PWM module and control module, and the PWM module and the VHDL language program is used to form the interface function module. A overall design discourse is conducted for the the software part, design processes of each function module are expounded in this paper. Finally the experimental results are given and they have been analysed. The experiment proves that the precision of SOPC technology in the application of electric motor drive control is high and the application is reasonable. It may become the trend of the development of the electric motor cars in the future.

Abstract: Pulse wave signal is analyzed in this paper especially the type I smooth pulse is selected to be further discussed. CPU is designed by using FPGA chips. This CPU contains various IP cores components, and can carry out multiple calculations and driving peripheral function. This paper implements the extractions the feature points of the specific pulse waves by using the CPU. The result of the design is basically ideal and achieves the expected target.

Abstract: SoPC technology provides a more convenient, flexible and reliable hardware and software co-design for embedded system design. In this paper we use this method in respect of software and hardware to design a new high performance hydropower on-line monitoring system. The device has been successfully integrated in the hydropower on-line monitoring system. The practical application confirms it has high performance, good stability, scalability, and the design method for power occasions other similar applications are also of great referential significance.

Abstract: A new high-speed infrared video-based fatigue detection system was developed using a system on a programmable chip (SoPC) in this study. Based on the limitations of PERCLOS, we merged the eyes and mouth fatigue related characteristics to improve detection accuracy, used a Difference of Gaussian (DoG) filter and Ada-boosting algorithm to implement driver fatigue detection based on multi-feature fusion. The detection system was produced using FPGA with a parallel processing structure and pipeline technology. This system is innovative and it can detect fatigued states efficiently and rapidly.

Abstract: Direct digital frequency synthesizer (referred to as DDS) is a kind of complete digital frequency synthesizer. In this article the principle of DDS were introduced. Set the design index of distortion and resolution, and design parameters of DDS in accordance with the index. DDS design describes by Verilog HDL, implement controlling four parameters of the waveform, frequency, phase, amplitude. Using FPGA and Quartus II/Nios IIwhich is Altera EDA software, realize DDS and its peripheral input / output and DA platform. The final direct to DDS simulation results and the overall DDS platform oscilloscope experimental data, verify the correctness of the design of DDS with the two data.

Abstract: SOPC technology of Nios II is Used for the design of intelligent digital photo frame in this paper. Developers can integrate design according to actual needs, fundamentally changing the lack of traditional design. Digital photo frame as a whole project is divided into two parts of the hardware module and software system. Functional correctness is verified by Quartus II, further downloaded to the FPGA for debugging, the observation results showed that digital photo frame has a high degree of freedom in the system optimization, which can be extended the life of the product on the market, greatly improving the performance of multi-function digital photo frame.

Abstract: A real-time image data acquisition and processing system based on SOPC in intelligent cart with automatic tracking function was designed. In this paper, the basic design theory and the system structure was analyzed. The Quartus II and Nios II software was used to make the system with real-time image acquisition function. And the data in SDRAM of two CMOS cameras based on SOPC was read. The design was tested with the system, and results showed that this module had the characters of design flexibility, fast image processing and expansibility.

Abstract: The system is based on DES/3DES, AES cipher algorithm as the research object.According to the characteristics of the algorithm, designs a configuration mode which can share resource in space and configurate algorithm in time. Then it uses hardware description language Verilog HDL to realize and optimize the design, and completes a custom reconfigurable DES/3DES/AES encryption/decryption IP core. By SOPC technology, the IP core, Nios II processor, network controller and other function. The design hardware structureis simple, flexibility, security, which can be widely used in the field of informationsecurity.