Papers by Keyword: SSD

Abstract: The impact of surface stress due to polish and grind processes on wafer bow was studied as a function of abrasive size. Results indicate that sub-surface damage from these processes can introduce significant surface stress. For polishing processes, this stress is proportional to mean abrasive size. The study also investigates stress as a function of depth below the wafer surface and finds that most stress is concentrated near the wafer surface.

Abstract: The flatness of a silicon carbide wafer in terms of bow and warp is the result of the combination of factors both material and process related. Sub-surface damage (SSD) from the wafering process steps can be considered as a thin film under compressive stress on the wafer surface. SSD is generally decreased with each subsequent processing step after the multiwire saw. Single-sided process steps can produce very different levels of SSD on opposing wafer surfaces, leading to high bow and warp values. The present study investigates the effects of SSD on wafer flatness at various process steps as well as methods to minimize shape effects due to SSD during and after processing.

Abstract: Data deduplication technology applied in solid state disks (SSD), can reduce the amount of write operations and garbage collection, and thus improve writing performance and prolong lifetime. With the significant increase of write performance onto SSD, whether deduplication based on SSD could be a performance bottleneck of SSD comes to a spot worthy of our attention. To this end, this paper, firstly, performs an experiment on achieving deduplication via software method, and reveals that software-based deduplication decreases SSD's read and write performance. And then a hardware-based deduplication with details is proposed and implemented to accelerate deduplication using FPGA, and expected results are achieved. Finally, we come to the conclusion that hardware-based deduplication can not only guarantee read and write performance of SSD, but also save storage capacity and enhance endurance.

Abstract: An implementation of a remote destruction solid state drive (SSD) was introduced in the design. The advanced technology of rapid data destruction, the technology of breakdown the flash with high-voltage pulse and the technology of GSM is combined together. As a result, user can operate through a simple command (text message or a call) to destroy all data in SSD, as long as the user confirms SSD is out of control. The method of erasing data and destroying the flash I/O are both executed, so the data can’t be recovered after destruction. At last, some tests are displayed to verify the performance of the remote destruction SSD.

Abstract: In this study, we present a novel internally hybrid SSD architecture (SMARC) which consists of both SLC and MLC flash memory packages, instead of only either SLC or MLC. By periodically migrating data between the two different portions (SLC and MLC space) according to running workloads dynamics, the proposed architecture is able to exploit their respective advantages complementarily to help overall performance, reliability and energy consumption. Our simulation results of a variety of workloads have shown that SMARC can improve the performance by nearly an order of magnitude, at the same time, significantly enhancing reliability and reducing energy consumption.

Abstract: In this paper, we analyzed the endurance of Nand Flash memory and then proposed a level adjusting scheme to use the MLC Flash dynamically to storage different amount of data levels through the entire lifetime. The result shows that the MLC SSD adopting this method could be totally written 4.8X more data than conventional MLC SSD and 16.5% more than SLC SSD.

Abstract: This paper presents a new architecture SSD based on NVMe (Non-Volatile Memory express) protocol. The NVMe SSD promises to solve the conventional SATA and SAS interface bottleneck. Its aimed to present a PCIe NAND Flash memory card that uses NAND Flash memory chip as the storage media. The paper analyzes the PCIe protocol and the characteristics of SSD controller, and then gives the detailed design of the PCIe SSD. It mainly contains the PCIe port and Flash Translation Layer.

Abstract: Optoelectronic Devices have obtained great interests for many decades. With the development of technology and in-depth research, the devices are scaled down rapidly, reaching sub-millimeter or even nanometer scale, and resulting in various new features. In recent years, a so called Self-Switching Device (SSD) which has diode-like I-V characteristics has attracted more and more attentions. Using Monte Carlo method, we have studied the electron transport in the self-switching device. Simulation results show that when the device size is smaller than the mean free path of electrons, the electron velocity is very different from that of larger device. The electron velocity and the energy become faster and higher, respectively. The reason of this phenomenon is explained by ballistic transport of electrons in the small size device. Since ballistic transport plays an important role in determining the behavior of electrons in small size device, it is need to be included in nanometer scale device modeling.

Abstract: NAND flash memory has been successfully employed in storage system due to its advantages such as performance, resistance, and capacity. NAND flash memory based solid state disk (SSD) has started to replace disk in numerous environments. However, the poor endurance offered by these SSDs continues to be their key shortcoming. To improve SSD endurance, we propose a static wear-leveling algorithm with variable threshold (WLVT). In contrast with traditional algorithm with fixed threshold, WLVT adjusts the value of threshold, so that each block can simultaneously reach the erasure times that the manufacturer gives when life of SSD is over. Therefore, available erasure time of each block will be fully utilized when SSD fails. Experimental results show that the endurance of the SSD is significantly improved.

Abstract: NAND Flash-based SSD has gained prevalence in enterprise and embedded system as storage device because its high I/O performance, low-power consumption, and Anti-vibration characteristics. RAID consisting of SSD can achieve higher performance. However, it brings new problems such as parity disks suffering from premature aging, data disk aging simultaneously. This paper based on the variation of SSDs reliability, design a new RAID-5 architecture with dynamic stripe length. It can effectively reduce the disk space overhead and improve the safety performance of the RAID.