Papers by Keyword: SSN

Abstract: A digital CMOS output interface circuit is proposed, which lowers down the peak and lengthen the duration of the pulse of current supplied by the power supply to reduce the SSN (simultaneously-switching noise) effects. The simulation shows that the maximal SSN voltage of the proposed circuit is 331.5mV compared to 662.4mV of the traditional one.

Abstract: To analyze the inhibition to SSN, we use the design and emulation tools from Ansoft Co., which are used in the optimization design on PDS, integrated with particular circuit designs. Firstly, the traditional means of adding Decoupling Capacitor is adopted to inspect and verify that increased decoupling capacitors will help to increase high frequency response. Secondly, we introduce a high impedance electromagnetic surface texture, which can be applied to decrease SSN. Lastly, we support that EBG is better than traditional adding decoupling capacitor.