Papers by Keyword: Schottky Barrier Diode

Abstract: The repetitive peak forward surge current (I_F,RM) is a practically important parameter for SiC Schottky diodes, as it ensures reliable and robust circuit designs. However, there is no established method and criterion for this imperative parameter. Manufacturers predominantly provide the non-repetitive peak forward surge current value (I_F,SM) in datasheets, which is generally determined from derated measured peak currents that cause diode failures. Consequently, it is assumed that I_F,SM enables diodes from various manufacturers with different structural designs to be compared in terms of their repetitive surge current performance. In this paper, we will demonstrate the need for a consistent criterion and a method to determine I_F,RM by analyzing repetitive surge currents in representative commercially available SiC Schottky diodes. The analysis is based on a recently proposed method and criterion for the repetitive peak surge current in SiC Schottky diodes that ensures the junction temperature does not exceed the maximum device rating, which is 175°C for the commercially available devices analysed in this study.

Abstract: The impact on doping profile, surface roughness and defect production of each process step for a suggested Multiple epitaxy and implantation (MEI) process for Super-junction has been investigated through Secondary Ion Mass Spectrometer (SIMS), Atomic Force Microscope (AFM), Deep Level Transient Spectroscope (DLTS) and Molten KOH etching. Results show that the suggested process can possibly reduce the cost of the original fabrication and speed up the process.

Abstract: This study focuses on analyzing the electrical performance and characteristics of Schottky Barrier Diodes (SBDs) on the carbon face (C-face) epitaxial layer. The C-face epitaxial layer is grown on monocrystalline 4H-SiC and has a thickness of ~ 11 μm. It displayed minimal surface roughness, with an R_q of ~ 0.3 nm. The C-face termination epitaxy was examined using grazing-angle X-ray photoelectron spectroscopy (XPS) analysis. SBDs were fabricated using a Ti/Al metal stack. Schottky Barrier Height (Φ_B) of about 1.2 eV was extracted from I-V measurements. Temperature-dependent I-V measurements demonstrated a forward voltage decrease as the temperature rises when the forward current is < 1 μA. However, for forward currents > 1 μA, the forward voltage increases with temperature. This rise in forward voltage could lead to a reduction in reverse recovery time and thus enhancing the switching speed. Additionally, the diode exhibits remarkable immunity to reverse leakage current up to 200 °C, surpassing the performance of the 6.5 kV JBS diode on Si-face 4H-SiC [1].

Abstract: This report describes the application of titanium nitride (TiN) with a silicon nitride (SiN) intervening layer as a Schottky electrode in a Schottky barrier diode (SBD) made of 4H-silicon carbide (SiC). This reduced the Schottky barrier height (Φ_b) to 0.74eV at room temperature, and it was confirmed that the reduction in Φ_b was due not only to the application of TiN but also to the intervening layer containing SiN at the SiC/TiN interface. Furthermore, TiN with SiN was applied to a device as a Schottky electrode, and the electric field reduction effect was verified by changing the high energy implantation and JBS width. As a result, the forward voltage (V_f) was found to be reduced by a maximum of 0.23 V while suppressing leakage current. The reason for describing the interlayer as “intervening layer containing SiN” is that there may be other substances besides SiN.

Abstract: The impact of silicon nitride (Si₃N₄) stress on 4H-SiC has been investigated. Current-voltage (I-V) measurements on Schottky barrier diode show that Si₃N₄ films thicker than 100 nm degrade both the ideality factor and Schottky barrier height. A 45-nm sacrificial oxidation effectively reduces defects from a 100-nm-thick Si₃N₄ layer, but defects persist with films over 300 nm. Interface state density of metal oxide semiconductor capacitor with a 44-nm-thick gate oxide confirms the effectiveness of sacrificial oxidation in mitigating defects.

Abstract: A systematic study is presented into the impact of a P₂O₅ surface passivation treatment, carried out prior to the deposition of a high refactory metal contact to 3.3 kV JBS diodes. Electrical results from Mo, W and Nb diodes reveal that those diodes that undergo the treatment have a major leakage current reduction, most significantly by 3.5 orders of magnitude to 1.5×10^-6 A.cm^-2 for treated W diodes. When applied to fully optimized 3.3 kV Mo/SiC JBS diodes, the P₂O₅ surface passivation treatment reduces the apparent barrier height, as well as the leakage current. SIMS analysis reveals that during the treatment, phosphorous diffuses into the top 10 nm of the SiC, achieving a peak density of 10¹⁹ cm^-3, while XPS results suggest some of this diffuses into the contact metal during the contact anneal, altering the SBH. TCAD simulations help give more insight into band diagram changes at the Schottky interface, where the partial activation of the phosphorous ions is shown to alter the Schottky barrier, promoting a thermionic field emission conduction, effectively lowering the barrier height at the interface in Mo/4H-SiC diodes.

Abstract: This paper discusses the design and simulation of 4H-SiC semi-SJ structures producing results that are below the unipolar limit, whilst also ensuring practical and cost-effective realisation. The results demonstrate that a semi-SJ structure with a 10° sidewall angle increases the implantation window of the device by 45%, relative to the full-SJ, whilst maintaining a high V_BD of ~2 kV and a low R_ON,SP. This design facilitates a wide implantation window with a reduced trench aspect ratio, significantly improving the practical realisation of the device. It also offers softer reverse recovery characteristics as a result of both the angled trench sidewall and the n-bottom assist layer (n‑BAL) which allows for the structure to be depleted gradually.

Abstract: In this paper, we present a new family of 3300 V silicon carbide (SiC) Schottky barrier diodes (SBDs) and power MOSFETs. The main design requirements are discussed with an emphasis on the design rules to improve the long-term reliability. Basic static and dynamic performance demonstrates low conduction and switching losses. Long-term tests such as high-temperature reverse bias (HTRB) and body diode forward bias stress were performed to evaluate the devices’ reliability. An emission microscopy (EMMI) study was conducted to assess the quality of the gate oxide. Outstanding surge and avalanche capabilities are reported with UIS ruggedness of 11.4 and 20.8 J.cm^-2 for SBDs and MOSFETs, respectively.

Abstract: Passivation treatments applied prior to Mo metallisation on Silicon Carbide (SiC) Schottky rectifier and metal-oxide-semiconductor capacitor (MOSCAP) structures are studied. A control sample and two treatments, comprising of an O₂ oxidation and a phosphorus pentoxide (P₂O₅) deposition, were studied. Electrical characterisation results show that P₂O₅ treatment improves the homogeneity of the diodes, with the ideality factor reducing to 1.02 and the leakage current reducing by three orders of magnitude to 2×10^-5 A/cm². Furthermore, the SBH was lowered by 0.11 eV and the variance of all the P₂O₅ treated Schottky characteristics over the batch reduced. Characterisation by X-ray photoelectron spectroscopy (XPS) showed that the stoichiometry, the Si:C ratio, of the SiC below the contact increased from 0.93:1 before treatment to 0.97:1 after P₂O₅ treatment.

Abstract: This paper discusses the study of 4H Silicon Carbide (4H-SiC) Schottky rectifier structures based on the superjunction (SJ) principle. The effects of device geometry have been investigated to optimise the trade-off between breakdown voltage (V_BD), specific on-resistance (R_ON,SP), and the ion-implantation fabrication window, so ensuring the final design is practically realisable. In this study, both full-SJ and semi-SJ (SSJ) layouts improve the V_BD-R_ON,SP trade-off to below the 4H-SiC unipolar limit. In comparison to a conventional planar Schottky diode, full SJ structures, with p-pillars that traverse the full length of the n-drift region, have a 7x improvement in R_ON,SP for a 50-100 V reduction in V_BD. In comparison, the SSJ structure is composed with the combination of the SJ structure and an n-bottom assist layer (BAL), which adds 2-μm of n-drift below the SJ pillars. The SSJ structure demonstrates a 5x improvement in R_ON,SP for a 300 V increase in V_BD, for the same aspect ratio. Most favourably, the SSJ structure also has an ion-implantation processing window 60% higher than the full SJ device, offering better anti-charge-imbalance characteristics. In both full and semi layouts, a trench sidewall angled (α) at 80^o was considered optimal, resulting in a slightly higher V_BD and R_ON,SP, and a wider processing window, compared to vertical (90^o) sidewalls.