Papers by Keyword: Si-Face

Abstract: We have developed a novel, material-lossless silicon carbide (SiC) wafer manufacturing process that eliminates the need for conventional grinding and polishing. Utilizing a thermal sublimation growth and etching technique called Dynamic AGE-ing^® (DA), we simultaneously performed thermal sublimation etching and growth on both the Si-face and C-face of single-crystal SiC wafers. This study investigated the impact of surface undulations—arising during DA planarization of as-sliced wafers with varying slicing qualities—on the densities of basal plane dislocations (BPDs) and in-grown stacking faults (IGSFs) in the epitaxial layers. Our findings demonstrate that larger pre-growth surface undulations correlate with higher BPD and IGSF densities in the DA-grown layers. By optimizing the initial wafer quality and DA process conditions, we achieved epitaxial layers with low defect densities (BPD density of 0.09 cm⁻² and IGSF density of 1.37 cm⁻²) without any material loss. This advancement offers a significant breakthrough in SiC device manufacturing, potentially reducing material costs and enhancing device performance by suppressing killer defects in the epitaxial layers.

Abstract: In conventional machining of SiC wafers, material loss and sub-surface damage (SSD) of both the front and back surfaces are major issues. In this study, we focused on Dynamic AGE-ing^® (DA), which is a sublimation-controlled process, and applied it to the total wafering process without any mechanical contact of both the front and back surfaces to explore the possibilities to reach the CMP-equivalent quality. DA process enables material lossless planarization of SiC wafers by applying a temperature gradient to achieve simultaneous etching and growth at the same rate on one and the other surfaces, respectively. To drive the planarization function for a multi-wire saw finished as-sliced wafer, as an example, a high-temperature regime above 2000 °C under an Ar background pressure higher than 1 kPa to suppress etching and growth rates was employed as the first step in the DA treatment. In this step, an effective annealing function arises where sublimation and recrystallization occur simultaneously through a sub-surface region on both sides of the wafer. Due to the active interchange of the surface and subsurface layer, a self-organizing planarization effect occurs on a macroscopic scale on both surfaces with the removal of SSD. The conventional DA processes were employed for the following microscopic flatness control. As a result, the roughness of the 6-inch as-sliced wafer was reduced to 0.7 nm on the Si-face and 2.0 nm on the C-face while maintaining the wafer thickness. This is the first promising result exhibiting the potential of thermal contactless treatment for next-generation wafer manufacturing by improving quality and cost.

Abstract: We study the interface properties of 4H silicon carbide Si-face 0001 and a-face 11220 power MOSFETs using the charge pumping technique. MOSFETs produced on the a-face show a higher electron mobility than Si-face devices, although their charge pumping signal is 5 times higher, indicating a higher interface/border trap density. We show the main contribution to the interface/border trap density on a-face devices originates from deep states in a wide range around midgap, whereas Si-face devices show a higher and exponentially increasing interface/border state density close to the conduction band edge of 4H silicon carbide, resulting in reduced mobility.

Abstract: Effects of residual oxygen in an annealing chamber on graphitization of SiC along with surface pre-treatment process have been investigated. As a pre-treatment process, SiO₂ was formed on 4H-SiC(0001) substrates by thermal oxidation before graphene formation annealing. Epitaxial graphenes were formed in several O₂ pressures and effects on graphitization of SiC were evaluated. It is shown that quality of graphene on SiC substrates which formed without pre-oxidation degraded by the presence of residual O₂ in the chamber. It is demonstrated that SiO₂ pre-oxidation films (about 10nm) were effective to prevent such degradations, for all O₂ pressures that we examined in this work. In addition, at O₂ pressure of 1.1x10^-1Pa, with SiO₂ pre-oxidation, a graphene growth rate was increased, which indicates that a certain level of O₂ pressure enhances graphene growth.

Abstract: In this paper, we present a comparison of defects in 4H-SiC epilayers grown on 4^o off-axis (0001) and (000-1) substrates. It was confirmed using high sensitive surface observation and micro-Raman spectroscopy that the generation of epitaxial defects on (000-1) C-face substrates was less susceptible to substrate morphological defects such as pits than that on (0001) Si-face substrates and 'comet-like' defects on (000-1) C-faces were caused by the inclusion of 3C-SiC. Moreover, PL imaging observation showed that stacking fault densities decreased when increasing the growth temperature, and they increased when increasing the C/Si ratio, irrespective of the face polarity. The densities, however, were lower for C-faces at higher growth temperature and C/Si ratio. The present results indicated that C-faces were preferable to Si-faces to achieve smooth step-flow growth suppressing epitaxial defects and stacking faults, which were influenced by the substrate morphological defects and the fluctuation of C/Si ratio in the epitaxial growth.

Abstract: This paper deals with the comparison of several MOS structures with different rapid thermal oxidation processes (RTO) carried out on Off and On-axis SiC material. A first set contains MOS capacitance structures on n-epitaxial layers, while a second set of MOS capacitance are built on p-implanted layers. Both sets include On and Off-Axis angle cuts. Furthermore, n-MOSFETs have been fabricated on On-axis p-implanted layers with the best oxidation process selected from the MOS capacitance study. The final objective is to show the performances of these On-axis p-implanted n-MOSFETs and to evidence the associated lower surface roughness at the SiO₂/SiC interface.

Abstract: In order to achieve high removal rate and high-quality processing on SiC wafer, we carried out the CMP processing experiment with the new type CMP machine (Bell-jar) by using the slurry with the addition of strong oxidant (KMnO₄). It was found that the high speed CMP processing was achieved by controlling the concentration of KMnO₄ in the slurry, the pH of slurry and the processing atmosphere. By using the slurry with the addition of KMnO₄ of 0.1mol/L, the removal rate was the fastest up to 1019nm/h in the fixed pH of 6. By use of the slurry of pH 3, the removal rate of C-face of SiC wafer was 1695nm/h On the other hand, the fastest removal rate of Si-face of SiC wafer was only 51nm/h by using the slurry whose pH is 7. In the open air atmosphere, the removal rate was 915nm/h, which was higher than that at the higher and lower atmospheric pressure.

Abstract: The sub-trenches in 4H-SiC Si- and C-faces could be disappeared by the thermal treatment in chlorine ambience at 900-1000oC. The surface morphologies of the thermally treated trench-sidewalls were unchanged. It is considered that the sub-trench is selectively removed because thermally Cl2 etching rate of the (0001) Si- and (000-1) C-face are different to the (11-20) and (1-100).

Abstract: Epitaxial graphene (EG) grown on SiC(0001) resides on the so-called buffer layer. This carbon rich (6√3×6√3)R30° reconstruction is covalently bound to the topmost silicon atoms of the SiC. Decoupling the graphene buffer layer from the SiC interface is a well studied topic since successful intercalation has been shown for hydrogen [1-3]. Recently, intercalation was also shown for oxygen [4, 5]. We present ARPES, XPS and Raman spectroscopy studies to determine the quality of oxygen intercalated buffer layer samples in terms of decoupling and integrity of the transformed graphene layer. The decoupling effect is demonstrated by ARPES measurements showing a graphene-like π band. XPS shows whether the oxidation takes place in the buffer layer or at the interface. Raman spectroscopy is well suited to investigate oxygen induced defects in graphene-like material.

Abstract: We demonstrate 4H-SiC bipolar junction transistors (BJTs) with an enhanced current gain over 250. High current gain was achieved by utilizing optimized device geometry as well as optimized surface passivation, continuous epitaxial growth of the emitter-base junction, combined with an intentional deep-level-reduction process based on thermal oxidation to improve the lifetime in p-SiC base. We achieved a maximum current gain (β) of 257 at room temperature and 127 at 250°C for 4H-SiC BJTs fabricated on the (0001)Si-face. The gain of 257 is twice as large as the previous record gain. We also demonstrate BJTs on the (000-1)C-face that showed the highest β of 439 among the SiC BJTs ever reported.