Papers by Keyword: SiO₂/SiC Interface

Abstract: We report the development of a low-temperature (600 °C) gate oxidation approach to minimize the density of interface traps (D_IT) at the SiC/SiO₂ interface, ultimately leading to a significantly higher channel mobility in SiC MOSFETs of 81 cm²·V^-1·s^-1, >11x higher than devices fabricated alongside but with a conventional 1150 °C gate oxide. We further report on the comparison made between the D_IT and channel mobilities of MOS capacitors and n-MOSFETs fabricated using the low-and high-temperature gate oxidation.

Abstract: For the improvement of a SiC/SiO₂ interface of SiC-MOSFET, we examined O₂ partial pressure (PO₂) controlled (OPC) oxidation process for the gate oxide formation. The OPC oxidation process has a potential to reduce interface state density (D_it) at SiC/SiO₂ interface by using appropriate PO₂ and oxidation temperature. However the process requires rapid thermal annealing which is not suitable for mass production. Thus we investigated the process using furnace. First, we optimized the OPC oxidation process for the furnace to realize low interface defect density. Secondly, we confirmed that reduction of D_it was determined by desorption of excess carbon in OPC process by the C–ψs measurement and X-ray photoelectron spectroscopy. Finally, a DMOSFET was fabricated using optimized OPC process. We measured the transfer characteristics, and found that the drain current with OPC was larger than without OPC process.

Abstract: Oxidized both silicon-face (Si-face) and carbon-face (C-face) wafers with various post-oxidation-annealing conditions were measured by scanning nonlinear dielectric microscopy (SNDM) and method for evaluating SiO₂/SiC interface quality using SNDM was investigated. We found that the normalized standard deviation of SNDM image was good parameter to evaluate SiO₂/SiC interface of Si and C-face. SNDM measurement does not need electrode fabrication to measure C-V curve, but needs just scan on the oxidized wafer with conductive tip, which is easier and quicker. This technique enables us to quickly examine the effect of variation of process parameters in MOS fabrication and to effectively reduce the time needed for R&D cycle.

Abstract: A new technique for local deep level transient spectroscopy (DLTS) imaging using super-higher-order scanning nonlinear dielectric microscopy is proposed. Using this technique, SiO₂/SiC structure samples with different post oxidation annealing (POA) conditions were measured. We observed that the local DLTS signal decreases with POA levels, which agrees with the well-known phenomena that POA reduces trap density. Furthermore, obtained local DLTS images had dark and bright areas, which is considered to show the trap distribution at/near SiO₂/SiC interface.

Abstract: SiO₂/SiC interface was investigated by using super-higher-order (SHO) scanning nonlinear dielectric microscopy (SNDM) with high spatial resolution. Comparison of non-oxidized and thermally oxidized 4H-SiC wafer (Si-face) revealed that only 5 min oxidation makes the interface quality spatially inhomogeneous. Next four SiC wafers treated under different post oxidation annealing (POA) conditions in NO ambient (three “with” and one “without” POA) were also compared. Using SHO-SNDM, local capacitance-voltage (C-V) curves were obtained. The local C-V curve obtained in sample with POA was more close to ideal C-V curve compared to the C-V curves obtained in the sample without POA. In addition, two-dimensional normalized SNDM images taken on the four SiC wafers were observed, which showed that the spatial deviation of interface state was reduced by the POA treatment. Moreover, standard deviations s of the normalized SNDM images were calculated. Then, very strong correlations between σ and interface-state density D_it as well as channel electron mobility μ_FE were observed.

Abstract: We present EDMR (electrically detected magnetic resonance) observations on “C-face defects” in C-face 4H-SiC MOSFETs. We found that negative threshold-voltage shifts of C-face MOSFETs are increased in association with EDMR signals of C-face defects as well as with the dissociation of hydrogen atoms induced by gamma-ray irradiation.

Abstract: Long-term degradation of MOS devices has to be avoided in different harsh irradiated environments, especially for aerospace or military applications. In this paper, an overview of the irradiation experiments recently performed on 4H-SiC MOSFETs having an oxynitrided gate oxide is given, with a special focus on the threshold voltage and the effective channel mobility drifts. The general mechanisms taking place during irradiation and post-annealing treatments are described. Finally, new open issues recently observed by performing the temperature measurement on irradiated MOSFETs will be introduced and discussed.

Abstract: This work presents the 10 MeV protons irradiation effects on 4H-SiC MOSFETs at different fluences. MOSFETs main electrical parameters, such as the channel mobility (µ_EFF), threshold voltage (V_TH), transconductance (g_m) and subthreshold current, were analyzed using the time bias stress instability (BSI) technique. Applying this method allowed us to study the effect of carriers interaction with generated interface traps, whether in the bulk or at the interface. Improvements, such as V_TH stabilization in time and a significant increase of the µ_EFF at high fluencies, have been noticed. We assume that this behavior is connected with the atomic diffusion from the SiO₂/SiC interface, towards the epilayer during proton irradiation. These atoms, in majority Nitrogen, may create other bonds by occupying various vacancies coming from Silicon and Carbon’s dangling bond. Therefore, by enhancing the passivated Carbon atoms number, we show that high irradiation proton could be a way to improve the SiO₂/SiC interface quality.

Abstract: The 4H-SiC MOSFET electrical response to 180 keV proton radiations at three different fluences has been evaluated. For a certain dose, the devices show an apparent improvement of their electrical characteristics likely due to the N and/or H atoms diffusion inside the oxide layer. This work complete our previous studies on high energy proton irradiation, showing that the 4H-SiC MOSFET is also robust to the low energy proton radiation, when the proton implanted range is located near the MOS interface.

Abstract: This paper deals with the comparison of several MOS structures with different rapid thermal oxidation processes (RTO) carried out on Off and On-axis SiC material. A first set contains MOS capacitance structures on n-epitaxial layers, while a second set of MOS capacitance are built on p-implanted layers. Both sets include On and Off-Axis angle cuts. Furthermore, n-MOSFETs have been fabricated on On-axis p-implanted layers with the best oxidation process selected from the MOS capacitance study. The final objective is to show the performances of these On-axis p-implanted n-MOSFETs and to evidence the associated lower surface roughness at the SiO₂/SiC interface.