Papers by Keyword: Silicon-on-Insulator (SOI)

Abstract: Core–shell Si/SiC nanostructures appear as promising building blocks for sensing applications, thanks to the high chemical stability of SiC coupled with the semiconducting properties of Si. In order to optimize the fabrication process of such structures, Si nanowires were coated with a thin SiC layer, and integrated as back-gated field-effet transistors. Two approaches for the fabrication of the SiC shell were then investigated. The first approach involves chemical vapor deposition of amorphous SiC on Si nanowires, without the need for masking; the second approach involves carbonization of Si surfaces to produce a thin crystalline SiC layer, but requires a larger thermal budget. The resulting structures were analyzed using high-resolution transmission electron microscopy (HR-TEM), and the devices were characterized electrically. Electrical characterization shows that the carbonization approach induces a dramatic decrease in drain-to-source current associated with gate leakage, whereas the electrical performances were preserved in the case of chemical deposition.

Abstract: Fabrication processes of a magneto-optic waveguide with a Si guiding layer for an optical isolator employing a nonreciprocal guided-radiation mode conversion are investigated. The optical isolator is constructed on a silicon-on-insulator (SOI) structure. The magneto-optic waveguide is fabricated by bonding the Si guiding layer with a cerium-substituted yttrium iron garnet (Ce:YIG). The relationship of waveguide geometric parameters is determined at a wavelength of 1550 nm. The results show that larger tolerance for isolator operation can be obtained at smaller gaps between Si and Ce:YIG. Bonding processes including photosensitive adhesive bonding and surface activated bonding are then compared. It is found that the surface activated bonding process is easier to control and more promising than the photosensitive adhesive bonding.

Abstract: This article presents a review of various methods for extracting the key parameters of junctionless (JL) MOSFETs, namely, the threshold voltage, flat-band voltage, doping concentration, carrier mobility, and parasitic series resistance. The applicability and limitations of different methods are analyzed using numerical simulations and experimental data for planar and tri-gate nanowire JL transistors with various nanowire widths.

Abstract: A micro biochemical sensor based on a SOI optical waveguide sensing platform is reported in this article. The sensing platform utilizes a Mach-Zehnder Interferometer (MZI) configuration. In order to satisfy the single-mode transmission condition of the waveguide and match the coupling size of standard single-mode fiber, a ridge waveguide structure is adopted to construct the MZI configuration. The key parameters of the waveguide are optimized by FDTD method. A process composed of contact exposure photolithography and Inductively Coupled Plasma (ICP) etching technology has been worked out for the fabrication of the optical waveguide sensing platform on SOI wafer. In the process, only one photolithographic mask is used. The mask is designed to have several patterns including an array of MZI configurations for multiple species sensing, a group of ridge waveguides with different key parameters as test references, and a group of geometric compensation schemes to test the methods of modifying the deviation which may arise during the ICP etching step. Process simulations are conducted to predict the exposure and etching results, which give strong support to the fabrication process control. Lithography problems including photoresist desquamation and line narrowing are solved to achieve the special structure.

Abstract: Sculptured or Bossed diaphragm is a specialized geometry with rigid center or boss. This paper presents the outcome of design approaches of sculptured diaphragm structure for low pressure applications. The simulation results are obtained using Intellisuite MEMS CAD design tool. The results indicate that sculptured diaphragm are designed with minimum thickness, compensating the large (a/h) ratio with local stiffening by means of rigid center and better linearity. Further, the maximum stress regions are analyzed for fixing the position of the piezoresistor. Finally, the sensitivity is improved by using the Silicon-On-Insulator (SOI) diaphragms.

Abstract: This paper introduces a novel SOI MESFET which enhancement breakdown voltage (VBR) by modifying electric field distribution. To achieve high enhancement of the VBR utilized three Silicon plates in buried oxide of the silicon on insulator metal semiconductor field effect transistor (SOI MESFET). This change in the SOI MESFET structure leads to controlled electric field distribution , increase VBR and Output Resistance (RO). The numerical simulation results show that the VBR of the Silicon Plates SOI MESFET (SP-SOI MESFET) structure improves by 50% compared with that of the conventional SOI MESFET (C-SOI MESFET) structure. As a result, the SP-SOI MESFET structure has superior electrical performances in comparison with the conventional structure.

Abstract: A ring resonator based on Silicon-on-Insulator (SOI) planar optical waveguide for micro biochemical sensor application is designed and simulated in this paper. The SOI optical waveguide is made with a ridge structure. According to the optical waveguide mode theory and the performance of the ring resonator, the size of the single mode ridge waveguide and the structure of the ring resonator are obtained. Based on the structure principle and the transmission mechanism of electric field of the ring resonator, the power transfer function and the parametric equation of sensitivity are derived. As a result, the value of Q of the ring resonator can reach 10³ magnitudes. At last, the structure and the transmission mechanism of electric field in the ring resonator are simulated in MATLAB software.

Abstract: The electron mobility in highly-doped junctionless (JL) nanowire (NW) silicon-on-isulator (SOI) MOSFETs with various nanowire widths is experimentally studied and analyzed. The evidence for the considerable enhancement of the effective electron mobility in narrow NW devices as compared to counterpart planar (wide) devices, having the same film thickness and doping, and as compared to the bulk silicon mobility with the same doping is presented. This mobility enhancement increases with decreasing the NW width. The reason for this effect is considered to be reduction of the impurity Coulomb scattering in narrow NW MOSFETs due to: (i) the reduced depletion-layer width; (ii) stronger screening of ionized impurities; (iii) the reduced number of neighbor ionized doping atoms per each free carrier in very narrow NWs. These results are of great importance since mobility degradation due to high doping was considered to be one of the most important limitations of the JL NW MOSFETs.

Abstract: Properties of Si/buried oxide (BOX) systems with bonded interface in silicon-on-insulator (SOI) wafers were studied in this paper. Results show impact of the starting Si material - Czochralski (Cz) or float-zone (Fz) grown silicon on the electron mobility (μ_e) and BOX charge behavior in ultrathin SOI layers. In particular, there were found: 1) the μ_e ~ N_e^-0.3 dependencies at the electron density N_e in the range of 4х (10¹¹-10¹²) cm^-2 in accumulation Cz-SOI layers with the μ_e degradation when Si thickness decreases from 20 to 9 nm, and 2) the ~ N_e^-0.6 behavior of mobility with no degradation in Fz-SOI layers. Raman spectroscopy shows the structural modification of Cz-SOI layers. An origin of degradation of the electrical and structural properties for ultrathin SOI layer is discussed.

Abstract: We present a single mask selective release process for complex SOI MEMS device. Comparing to the one-step dry release process, there are two improvements, the first one is to ensure that the bottom of the suspension beams will not be notching, and have sufficient strength and rigidity, the second one is to ensure that the released structures will not be damaged during wafer dicing. According to the proposed design rules, in the dry release step, most of the device area is released, except the boundaries of the proof mass and the suspension beams. Then, in the wet release step, all the structures will be released, and also increased the gap below the structure. So the suspension beams is protect enabled that the device has sufficient rigidity and not easy to break. To verify this method, a micromachined gyroscope is fabricated and test.