Papers by Keyword: Silicon-on-Insulator (SOI)

Abstract: SOI Ridge nanowire waveguide (RNW) has advantages of strong confinement of optical mode, low propagation loss, small bend radius and fully compatible with CMOS technique, etc. An ultra-compact Y-branch coupler based on SOI RNW was designed and fabricated. Based on the finite-difference beam propagation method (FD-BPM), key parameters of the coupler were analyzed. Then the device was fabricated by electron beam lithography (EBL) and inductively coupled plasma (ICP) reactive ion etching. Results showed that the propagation loss of RNW was 1.89 dB/mm, and the radiation loss of the coupler with branch angle of 30° was only 0.66 dB. Compared with traditional Y-branch coupler, the proposed structure were more promising for high density optical integrated circuits.

Abstract: With the extensive research and application of SOI nano-optical ring resonators, the problem of high integration becomes the bottleneck restricting its development. To research the effect of deposited SiO2 insulating layer on the resonance characteristic of SOI nano-waveguid ring cavity while integrating, a rib waveguide ring resonator with 500nm SiO2 insulating layer deposited was designed and fabricated in this paper. By testing the resonance transmission spectrum power of this structure, it is found that SiO2 insulating layer deposited has no effect on the grating vertical coupling efficiency while improves the quality factor to 14.000±1.000.

Abstract: An optical biosensor with a slot-waveguide-based micro-ring resonator on silicon-on-insulator (SOI) is reported. By numerical analyzing, a small-sized sensor of 25×15μm² with a sensitivity of 594nm/RIU can be achieved for NaCl solution, which is about eight times of that of the conventional micro-ring sensor. The free spectral range of 25.6nm and a quality factor Q of 430 are also observed. If SNR is more important, an asymmetric coefficient of 0.7 can be introduced to enhance Q factor. Our analysis also shows that the sensor has good sensing characteristics to other organic solutions.

Abstract: We design a double slots based on micro-ring resonator on silicon-on-insulator (SOI). An asymmetric structure is considered for the ring waveguide in order to improve the sensor's bending efficiency. Finite-difference time-domain (FDTD) method is used to analyze and optimize this sensor. The optimized size of the sensor is below 25×15μm². Numerical analysis shows that when the radius of the micro-ring is about 5μm, the sensitivity reaches a value of 708nm/RIU, which is ten times of that of the conventional micro-ring sensor. Quality factor (Q factor) of 580 and free spectral range (FSR) of 33nm are also obtained. Our analysis also shows that the sensor has good sensing characteristics to different organic solutions.

Abstract: We investigated the formation of nanopores on top Si layers of silicon on insulator substrates by CH₃SiH₃ pulse jet chemical vapor deposition. Nanopores were obtained by chemical etching of the buried oxide layer below the pits which were introduced during the SiC growth. The high nanopore density was obtained when the SiC growth temperature was set at 925 °C. The nanopore density gradually decreased with increasing the temperature at higher SiC growth temperature. The pore size increased with increasing the SiC growth temperature. These results suggest that pore density and size strongly depend on the SiC growth temperature.

Abstract: In this work, we have investigated the fabrication of Double gate and Single gate Junctionless silicon nanowire transistor using silicon nanowire patterned on lightly doped (10⁵ cm^-3) p-type Silicon on insulator wafer fabricated by Atomic force microscopy nanolithography technique. Local anodic oxidation followed by two wet etching steps, Potassium hydroxide etching for Silicon removal and Hydrofluoric acid etching for oxide removal, were implemented to reach the structures. Writing speed and applied tip voltage were held in 0.6 µm/s and 8 volt respectively for Cr/Pt tip. Scan speed was held in 1.0 µm/s. The etching processes were elaborately performed and optimized by 30%wt. Potassium hydroxide + 10%vol. Isopropyl alcohol in appropriate time, temperature and humidity. The structure is a gated resistor turned off based on a pinch-off effect principle, when essential positive gate voltage is applied. Negative gate voltage was unable to make significant effect on drain current to drive the device into accumulation mode.

Abstract: A slope SOI-LDMOS power device is proposed for high-voltage. When a positive bais is applied to the drain electrode, holes are induced and astricted by the slope buried oxide layer. So a high density positive charge layer is formed on the buried oxide layer. The electrical field in the buried oxide is improved as well as vertical breakdown voltage by the layer. Because the thickness of the drift region linearly increases from the source to the drain, the surface electric field is optimized, resulting in increase of lateral breakdown voltage. In this paper, the electric characteristics of the new device are simulated by Medici softerware. The result is shown that above 600 V breakdown voltage is obtained at 1μm thick buried oxide layer. The breakdown voltage is higher by three times than that of conventional SOI LDMOS.

Abstract: In the present study, the pursued purposes were: (i) monitoring the electrical properties of silicon-on-insulator nanowires (SOI NWs), (ii) determination of surface treatments suitable for obtaining reproducible states on the surface of SOI NWs after their long-term storage, and (iii) identification of surface treatments suitable for regenerating the NW surface after protein (bovine serum albumin molecules) detection. It is shown that, during storage, with the passage of time a negative effective charge was accumulated on the surface of n-SOI NWs up to surface density Q_eff = (2-4)х10¹² cm^-2, while the interface states at the NW/SiO₂ interface underwent relatively slow depassivation. Treatments in H₂O₂ with subsequent treatments in HF can be used for removing organic contaminations from the NW surface and for regenerating the initial working state of SOI NWs after protein detection.

Abstract: The effect of the free carrier absorption loss on the split-ridge waveguide based phase modulator is analyzed at 1.3 and 1.55 µm. The electrical device performance is predicted using the 2-D semiconductor package SILVACO software under DC operation. Based on the simulation results, it is shown that there is a penalty of increased free carrier absorption as the injected electrons and holes are getting higher. Meanwhile, the loss of the device at 1.3 µm is smaller than that of 1.55 µm at an equal applied voltage.

Abstract: The analyses of the simulation of a single mode buried waveguide optical phase modulator based on SOI material are here reported. The structure has been simulated by Athena from Silvaco simulation package. The buried waveguide is created by doping phosphorus with concentration of 10e15 cm-3 into the substrate. The real refractive index and the absorption coefficient of the waveguide are changed using the free carrier dispersion effect via carrier injection of a pn junction. The efficiency, VπLπ is calculated and the performance is compared with that of the rib waveguide optical phase modulator of the same material and dimensions. Simulation shows that the device can be an efficient device for application in intensity modulation.