Papers by Keyword: Silicon Carbide (SiC)

Abstract: The deployment of silicon carbide (SiC) power devices in aerospace applications is constrained by their unexpected susceptibility to single-event effects (SEEs), despite the inherent advantages of wide bandgap materials. In this work, we experimentally investigate the SEE mechanisms in in-house fabricated 1200 V SiC VDMOSFETs under heavy-ion irradiation using Ta ions with a LET of 75 MeV·cm²/mg. Real-time current monitoring, post-irradiation electrical characterization, and focused ion beam (FIB) analysis were employed to systematically examine device degradation and failure modes under various bias conditions. The results demonstrate a clear progression of damage with increasing bias voltage: no significant changes, single-event gate leakage degradation (SEGLD) at 100 V, single-event leakage current (SELC) in both I_d=I_g and I_d>I_g modes at 300–400 V, and catastrophic single-event burnout (SEB) at 500 V. Structural analyses reveal progressive deepening of gate oxide fractures, extension into the P+ source region, and eventual source metal melting, consistent with the observed electrical degradation. Notably, the threshold voltage remained stable throughout, suggesting that localized damage to limited unit cells has minimal influence on the global device threshold. These findings provide critical insights into SEE-induced degradation pathways in SiC MOSFETs and offer valuable guidelines for the design and radiation hardening of next-generation aerospace power systems.

Abstract: Silicon carbide (SiC) has emerged as a leading material for high-power applications. However, the high density of interface states (D_it) at the SiO₂/SiC interface still constrains the performance and reliability of MOSFET devices. In this work, lateral 4H-SiC MOSFETs subjected to post-deposition annealing (PDA) in nitric oxide (NO) of different durations were investigated through capacitance-voltage measurements, supported by an analytical model and an iterative MATLAB-based D_it extraction algorithm. The results demonstrate that NO PDA effectively reduces D_it not only near the conduction band edge but also towards the valence band, yielding improved channel mobility (µ_FE) and enhanced threshold voltage stability.

Abstract: A charge-imbalanced P-pillar distribution termination (D3) is proposed for 1500 V-class 4H-SiC superjunction (SJ) devices. By combining a junction termination extension (JTE)-based termination with gradually widened P-pillar spacing, the design effectively suppresses edge electric field crowding and enhances device reliability. TCAD simulations show that D3 achieves comparable blocking capability while exhibiting significantly improved robustness against charge imbalance, oxide charge density, and JTE dose deviations, demonstrating superior process margin and reliability. With relaxed process sensitivity and an efficient structure, D3 presents a promising approach for high-voltage 4H-SiC SJ device fabrication.

Abstract: We experimentally demonstrated a ~2x on-current enhancement in VDMOSFET fabricated in a standard 3300 V-rated 4H-SiC process. The on-current improvement is achieved by applying a positive bias to the p-well region when the VDMOSFET is in the on-state. A 5x10³-10⁴ ratio between the on-current gain and the p-well current gain is shown. TCAD simulations are performed to study the underlying mechanisms of the on-current gain.

Abstract: This work reports enhanced high-voltage blocking capability and an enlarged process window for junction termination extension (JTE) in SiC power devices using a hybrid random and channeling implantation for p-type doping (Al), compared with conventional random-only implantation. A three-step hybrid implantation process has been developed to replace a nine-step random implantation, achieving a similar doping profile and equivalent breakdown voltage in the JTE while significantly increasing fabrication productivity and reducing cost. Moreover, TCAD studies reveal that when using the same number of steps and ion energies as the conventional random implantation method, the JTE realized by the channeling-incorporated hybrid approach enables an increased breakdown voltage and a widened dose window in SiC devices. This is attributed to a deeper Al distribution with a lower average concentration, which effectively alleviates electric field crowding.

Abstract: In this paper, the radiation resistance of GaN and SiC is compared. The effect of the irradiation temperature on the carrier removal rate in both semiconductors during proton irradiation is considered. It was found that in GaN, as well as in SiC, the rate of carrier removal decreases with increasing irradiation temperature. The dependence of the GaN sample resistance on the radiation dose was also calculated based on a model previously proposed to describe a similar dependence for SiC. Based on the experimental data obtained, it is concluded that the processes of radiation compensation in GaN and SiC are similar.

Abstract: Paralleling SiC MOSFETs in high-power modules introduces overvoltage and oscillation risks due to parasitic capacitances and inductances. This study presents a 200 kW EV inverter module co-designed at the device and packaging level to ensure switching reliability under harsh automotive conditions. At 800 V, the planar SiC MOSFET maintained stable gate voltage, while a benchmark trench device module experienced severe ringing and failure. Kelvin-source structures and internal gate resistors mitigated parasitic turn-on, and device-level optimizations—including a 0.5 µm foundry technology, silicide gate, and hexagonal cell layout—improved body-diode performance, together with the channel mobility, blocking voltage, and minimized on-resistance and switching losses. The resulting AEPR25B12C1STJN module demonstrated effective resonance damping, matched the performance of commercial trench module FS03MR12A6MA1B in static and dynamic tests, and achieved 98% AC efficiency with over 200 kW output at 150 °C junction temperature.

Abstract: In this work, the power cycling capability of discrete SiC MOSFETs of seven manufacturers is investigated. The results show that even nominally similar devices can exhibit substantially different power cycling capabilities. The differences among the tested devices involve the scaling factor and the slope of the lifetime curves, but also the dependence of the baseline temperature. Furthermore, some devices exhibit a considerable increase in power cycling performance towards lower temperature swings, which cannot be characterized properly by power cycling tests at typical test conditions with much larger temperature swings. Thus for a proper assessment of the power cycling performance, multiple tests at suitable test conditions are necessary to obtain meaningful results.

Abstract: We report on the development and systematic validation of an ultra-pure silicon carbide (SiC) source material specifically engineered for physical vapor transport (PVT) growth of optical-and electronic-grade single crystals. The material is synthesized by chemical vapor deposition (CVD) using high-purity chlorosilane and methane precursors, yielding dense, void-free polycrystalline 3C-SiC with precise 1:1 stoichiometry. Over more than two years of continuous production, bulk metallic impurities across 17 monitored elements were consistently maintained below 100 parts per billion by weight (ppbw), with most batches achieving <50 ppbw. Surface metals, assessed after proprietary crushing and cleaning processes, were similarly controlled to <100 ppbw. Nitrogen levels, determined by secondary ion mass spectrometry (SIMS), remained stable in the low 10¹⁵ cm⁻³ range, enabling semi-insulating or precisely doped crystal growth. Purity and reproducibility were verified by a cross-technique analytical approach including glow discharge mass spectrometry (GDMS), and inductively coupled plasma mass spectrometry (ICP-MS). Microstructural investigations confirmed dense, void-free grains and high crystallographic uniformity. With production capacity scaling toward 60 tons per month, this CVD-based SiC source material establishes a robust platform for next-generation PVT growth. Its combination of ultra-low contamination, structural integrity, and scalable manufacturing positions it as a key enabler for optical SiC applications such as transparent wafers for augmented reality (AR) systems, as well as advanced power and RF devices.

Abstract: Suppressing the expansion of Single Shockley-type stacking faults (1SSFs) is critical for the growing demand of high-performance power devices. However, the underlying suppression mechanism has not yet been fully elucidated. Through proton ion implantation studies, we have established a fundamental approach by modeling this phenomenon. Carbon vacancy (V_c) generated by high-energy proton implantation are found to play a significant role in suppressing the expansion of 1SSFs.