Papers by Keyword: Silicon Carbide (SiC)

Abstract: Silicon carbide is a leading wide-bandgap semiconductor for high-voltage power electronics. For 6.5–10 kV operation, thick epitaxial layers (≥60 µm) are required to sustain depletion width and maintain uniform electric fields, placing a premium on low extended-defect densities in both substrate and epilayer. Thick epitaxial 4H-SiC layers of 60 µm and 110 µm were grown on 6-inch substrates in a multi-wafer warm-wall reactor and evaluated by synchrotron X-ray topography in grazing-incidence (22-4 16) and transmission (11-20) geometries. Transmission imaging showed substrate dislocation content near the lower bound typically reported for 6-inch wafers. Notably, grazing-incidence topography (penetration depth >40 µm) revealed no basal-plane dislocations propagating into the epilayers, consistent with efficient dislocation conversion at the substrate–epilayer interface. The 3C-SiC inclusion density was ~30 per 6-inch wafer for 60 µm epilayers and ~60 per wafer for 110 µm epilayers; the average micropipes density varies from 0 to 5 for both 60 and 110 um epiwafers. Threading dislocation densities—screw, edge, and mixed—were on the order of 1.0–2.0 × 10³ cm⁻². These results establish thick 4H-SiC epilayers with suppressed basal-plane propagation and substantially reduced extended-defect content, providing a strong basis for reliable 6.5–10 kV device fabrication.

Abstract: Micropipe defects in silicon carbide (SiC) materials significantly degrade the performance of SiC materials and their applications in semiconductor devices. In this study, systematic methods were utilized to characterize different micropipes in 4H-SiC. X-ray topography was employed to investigate the morphology of micropipe defects in SiC substrates and quantify their associated lattice distortion fields. Meanwhile, white light interferometry mode microscopy and inner stain were utilized to thoroughly characterize their properties. It was found that micropipes were accompanied with different size and distortion areas in SiC substrate. This work will be served as a refined characterization of micropipes and give guidance for device application for SiC substrate.

Abstract: The increasing demand for Al7075 metal matrix composites (MMCs) stems from their exceptional characteristics, which include a high strength-to-weight ratio, low density, and superior mechanical characteristics. This research focuses on strengthening the Al7075 aluminum alloy by incorporating silicon carbide (SiC) and graphite particles. The material was produced through stir casting, using constant weight proportions of 3% SiC and 7% graphite. The research investigates the machinability of the stir-casting fabricated Al7075-SiC-Gr composites through turning operations under dry cutting conditions. Key process parameters include cutting speed (520, 840, 1200 RPM), axial feed rate (0.15, 0.25, 0.35 mm/rev), and doc (0.1, 0.2, 0.3 mm) were varied to assess their impact on power consumption. Results indicate that power consumption rises with increased cutting speed and doc. Among the factors, machining speed significantly affects power consumption, contributing 2.74% to the increase in power usage. This study highlights the vital role of machining parameters in optimizing the performance of Al7075-SiC-Gr MMCs and provides insights for enhancing both efficiency and surface quality in manufacturing applications.

Abstract: With its excellent thermal conductivity, high critical breakdown field strength, and high temperature tolerance, Silicon Carbide (SiC) is widely used in the fabrication of power devices. In recent years, many vertical high-voltage SiC PiN diodes with superior performance have been reported. However, since the cathode-anode voltage in these devices is vertically blocked in the semiconductor, the on-chip isolation between the devices is difficult to achieve. For this reason, the vertical power device is typically employed for high power densities in single-device packages or power modules. In contrast, effective isolation between lateral high-voltage devices can be achieved by using isolation structures, which enables monolithic integration with lateral PiN diodes, transistors, and resistors to achieve control, routing, and power density regulation in smart power-integrated circuits (ICs). This work describes the design and fabrication process of a novel SiC high-voltage lateral PiN (HVLPN) diode with the addition of a lateral isolation structure with a thickness of 10 μm to achieve sufficient isolation between breakdown voltages and devices, as well as a solution for the deep etching of the SiC over 10 μm with a thick enough Hard Mask (HDM), which is required for the actual fabrication process.

Abstract: This work presents simple layout configurations for current sensing resistor networks to measure fast and high currents in SiC devices. The proposed layout reduces the inserted inductance in the switching loop when compared to coaxial shunts, which is key for the application of SiC devices in space. High inductance in the switching loop leads to dangerous overshoots during turn-off transients, that can block the adoption of SiC devices in space due to single event burnouts. After presenting the different proposed layouts, the inserted inductance of each one is measured with an impedance analyzer as well as performing switching tests. Applying field cancellation techniques in the layout of a simple parallel resistor network, the inserted inductance is reduced up to 17.6 % when compared to a coaxial shunt, while obtaining the same current sensing performance.

Abstract: In this work, a comparison of standard bulk 4H-SiC epi wafers and Soitec's SmartSiC™ wafers as well as the influence of RTA processing was conducted. For this, MOS capacitors were processed using thermal gate oxide paired with a polycrystalline gate electrode. Subsequent High temperature steps were avoided until an RTA process was performed on some of these wafers. To investigate the oxide quality on all wafer and process splits, CV-, time-zero dielectric breakdown and constant-current stress time-dependent dielectric breakdown measurements were carried out. For the examination of bulk wafers and SmartSiC™, no relevant differences in terms of yield, oxide quality, interface state density and reliability were found. In contrast, RTA processes seem to create a shift in flat band voltage and also lead to a reduction in oxide lifetime. The V_FB shift could partially, but not completely, be explained by addition activation of dopants in the polysilicon electrode. The influence on the oxide reliability, however, is still unclear.

Abstract: This study focuses on the trench etching process for the fabrication of SiC Superjunction Schottky diodes, utilizing an ICP-RIE technique. Through a series of experiments, we optimized the etching parameters, including ICP power, RF power, and SF₆ gas flow rates, to achieve etching rates ranging from 157 nm/min to 372.1 nm/min. Additionally, the study identified the performance of the hard mask as a critical issue during the etching process, which was improved by reducing the RF power below 80 w. The deepest trench achieved reached a depth of 21 μm at 75 w RF power, 1000 w ICP power and 40 sccm SF₆, confirming the feasibility of this approach for fabricating high-performance SiC superjunction devices.

Abstract: Currently, silicon carbide (SiC) is widely recognized as a wide bandgap semiconductor, with expanding applications in harsh environments, such as high temperature and radiation exposure. In this study, we fabricated a planar structure 4H-SiC gate-all-around junction field-effect transistor (JFET), wherein the channel region is formed through ion implantation at varying doses. We successfully produced both normally-on and normally-off JFETs. Moreover, we constructed a JFET commonsource amplifier. The amplifiers achieved a maximum gain of -226.7 (47.1 dB) at a supply voltage of V_DD = 30 V.

Abstract: This study investigates the role of the electrical failure of the SiO₂ film in the breakdown of SiO₂/ZrO₂ and SiO₂/HfO₂ stacks. Our findings indicate that the breakdown is governed by the SiO₂ film, regardless of its thickness. This highlights the importance of carefully considering the interfacial SiO₂ layer when using high-k materials in SiC devices. We demonstrate that thicker SiO₂ layers offer several benefits, including reduced leakage, enhanced thermal stability and electrical strength, and decreased trapping. In contrast, stacks with thinner SiO₂ have a higher effective k value, exploiting the benefits of high-k dielectrics. Our experimental results suggest that a 7 nm SiO₂ layer underlying 30 nm crystalline ZrO₂ or HfO₂ provides optimal performance. Furthermore, we present calculations that reveal the trade-off between SiO₂ thickness, k value, and breakdown voltage for a 50 nm thick dielectric stack. Our results imply that a k value exceeding 20 does not yield significant benefits in 50 nm thick SiO₂/dielectric stacks.

Abstract: In this study, we developed an ion implantation process to create a P-type junction isolation (P-iso) structure, which effectively isolates CMOS and 1700-V VDMOSFET devices on a single 4H-SiC wafer. To ensure a sufficiently high blocking voltage and to prevent punch-through or reach-through in all p-n junctions during operation, Sentaurus TCAD was used to optimize the conditions for the P-well, N-well, P-iso region, and multi-floating zone (MFZ) design. A high-energy ion implantation, reaching up to 2.5 MeV, was then conducted to verify the breakdown voltage (V_BD) of the P-iso and MFZ structures. Experimental verification confirms a breakdown voltage (V_BD) exceeding 2000 V.