Authors: Yuma Obayashi, Urara Satake, Toshiyuki Enomoto
Abstract: With the ever-growing demand for further increase in the integration density of semiconductor devices, silicon wafers as the substrates for most devices are required to be extremely flat. In particular, it is strongly required to suppress edge roll-off, which seriously deteriorates the surface flatness near the wafer edge during polishing process in the final stage of the wafer manufacturing. In this study, we investigate the properties of polishing pads required for decreasing edge roll-off and propose the evaluation method of the properties. Polishing experiments with silicon wafers and evaluation tests for polishing pads reveal that the proposed method can estimate the obtained edge surface flatness.
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Authors: Jumpei Kusuyama, Shintaro Iwahashi, Takayuki Kitajima, Nagahisa Ogasawara, Akinori Yui, Hirotsugu Saito, Alexander H. Slocum
Abstract: Increasing the wafer diameter from φ300 mm to φ450 mm is required to enhance semiconductor devices productivity. A high-stiffness rotary grinding machine equipped with water hydrostatic bearings was developed for a φ450 mm silicon wafer. The grinding machine has an upper structure consisting of a wheel spindle system and a lower structure consisting of a rotary worktable system. The spindle shaft creates both rotary and axial feeding motion. The upper and lower structures are clamped together rigidly by three kinematic couplings. A higher loop stiffness is required for the grinding machine because grinding the larger wafer requires a higher grinding force. This paper investigates the loop stiffness of the developed wafer grinding machine.
655
Authors: Rong Chen, Ai Suo Pang, Shuai Li, Bao Dian Fan, Jiang Hui Zheng, Qi Jin Cheng, Chao Chen
Abstract: A YAG continue-wave laser has been used to refine the surface of silicon wafers in this study. During laser scanning, the irradiated region of the surface of the wafer experienced melting and subsequent recrystallization, which results in a redistribution of metal impurities in the molten pool along the depth direction. Cross-sectional micrographs of irradiated wafers have a clear boundary, which confirms the process of recrystallization, and the depth of molten region depends on the scanning parameters and the size of wafer. Secondary ion mass spectrometry measurements have been carried out to characterize the concentration of metal impurities. After redistribution of metal impurities, a final relative purity region was formed close to the surface. SIMS measurements demonstrate that the metal impurity concentration of the purity region has significantly reduced. The mechanism of the redistribution process of metal impurities in the molten pool has been qualitatively analyzed. All of the experimental results support that the CW laser scanning technology can effectively refine the specific surfaces of silicon wafers, and this technology has a great potential in the field of solar cells.
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Authors: Ji Xiang, Xiao Jun Guan, Jin Wang
Abstract: In order to investigate the effect of annealing temperature on oxygen clusters’ evolution in silicon wafer during low temperature annealing, a phase-field model and it’s algorithm were established, and the changes of the oxygen clusters’ structure, amount (concentration) and sizes were simulated at different annealing temperature. The results show that when the temperature varies from 923 to 1023K, the oxygen clusters with reasonable amount and average size can be gained; when the temperature is too higher or lower, the suitable oxygen clusters cannot be found; it is verified that the established model and its algorithm have credible thermodynamics and experimental basis.
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Authors: Yu Chen Zhao, Carl Labergère, Benoit Panicaud, Jean Luc Grosseau-Poussard, Philippe Goudeau
Abstract: The Smart-Cut technology consists in the increasing of pressure imposed by the diffusion of hydrogen ions in the silicon substrate leading to a wafer splitting. In the present work, we studied the evolution of the stress field in the crystalline lattice of silicon, the diffusion of hydrogen ions as well as the growth and coalescence of cavities. Meanwhile, we test several models and simulate these phenomena by a numerical approach, in order to compare its results to experimental observations.
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Authors: Masahiko Yoshino, Yohei Shimizu, Kentaro Kono, Motoki Terano
Abstract: In this paper, machining tests of silicon wafer under high hydrostatic pressure are reported. A lathe type machining tester was developed, and machining tests were conducted on the upper surface of silicon wafers whose crystal orientation was (001). Roughness of the finished surface was measured by using AFM, and the effect of hydrostatic pressure on roughness was studied. It was found that roughness decreases with increase of hydrostatic pressure. It was also found that the roughness depends on the cutting direction. The roughness is large when the cutting direction is parallel to the <100> direction, but it is small when the cutting direction is parallel to the <110> direction. Mechanism of effects of hydrostatic pressure and crystal orientation are discussed.
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Authors: Chin Lin Hsu, Shyankay Jou, Ying Ji Chuang, Ching Yuan Lin
Abstract: Si Wafer, pre-weathered TiZn alloy (TiZn-P), Aluminum (Al), and hot-dipped galvalume steel (G.L.) are chosen in this work for the study of hydrophobic coating to various substrates. Various amounts of TS-720 hydrophobic nanoparticles were mixed into ITRI hydrophobic agent (H.A.), and this mixture liquid was applied onto different material surfaces by using a coating bar technique. High contact angle near 140o are achieved in all samples with 2.5 wt% TS-720 in ITRI H.A. mixture.
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Authors: Ren Ke Kang, Yan Fen Zeng, Shang Gao, Zhi Gang Dong, Dong Ming Guo
Abstract: Wire saw process is widely used in the machining of hard and brittle materials with low surface damage and high efficiency. Cutting of silicon wafers in integrated circuit (IC), semiconductor and photovoltaic solar industries is also generally using wire saw process. However, the surface layer damage induced by wire saw process will seriously decrease the wafer quality and increase the process time and production costs of the post grinding and polishing. The surface layer qualities of the silicon wafers sawed by the different wire saw processes was investigated in this paper. The characteristics of surface roughness, surface topography and subsurface damage of silicon wafers sliced by the fixed abrasive and the loose abrasive wire sawing respectively were compared and the corresponding reasons were analyzed.
685
Authors: Shenq Yih Luo, Tsung Han Yu
Abstract: The purpose of this paper was to investigate the silicon wafer surface roughness ground by the micro pellet grinding tool and the electroplated disc grinding tool with diamond grit size of 4-6 μm and 10-20μm under the spindle rotation speed of 500-2500 rpm and the feed rate of 1-5 μm/min. The results showed that the micro pellet grinding tool can get a better surface roughness of the silicon wafer than the electroplated disc tool. When the tools containing a larger diamond grit were employed, selecting a higher spindle rotation speed and a lower feed rate can obtain a better wafer roughness. However, when the tools of a smaller diamond grit were used, the spindle rotaion speed operates properly at a optimal value to obtain a best wafer surface roughness, which achieves Ra = 0.03-0.06 μm for the micro pellet tool. Besides, the material removal mechanism during the grinding silicon wafer for these two tools displayed mainly ductile grinding behavior.
273
Authors: Abdul Rahim Mahamad Sahab, Nor Hayati Saad, Amirul Abdul Rashid, Yusoff Noriah, Nassya Mohd Said, Ahmad Faiz Zubair, Ahmed Jaffar
Abstract: Silicon wafer is widely used in semiconductor industries for development of sensors and integrated circuit in computer, cell phones and wide variety of other devices. Demand on the device performance requires flatter wafer surface, and less dimensional wafer variation. Prime silicon wafer is hard and brittle material. Due to its properties, double sided lapping machine with ceramic grinding agent were introduced for machining high quality standard silicon wafers. The main focus is the silicon wafer with high accuracy of flatness; to reduce total thickness variation, waviness and roughness. In this paper the lapping experiment and analysis showed that the double sided lapping machine is able to produce total thickness variation less than 10 um at controlled process parameters within short processing time. Machining using low mode method reduced the total thickness variation (TTV) value. The lapping load and speed directly reflected the performance and condition of final silicon wafer quality.
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