Papers by Keyword: Stacking Fault

Abstract: This work explores the role of implantation depth in suppressing bipolar degradation of 4H-SiC PiN diodes through proton implantation. Targeting depths aligned with active basal plane dislocations (BPDs) effectively reduces stacking-fault expansion, as confirmed by electroluminescence imaging [1,2]. From these observations, we quantified the effective range of suppression in both depth and safe operating current density. Room-temperature proton implantation (170keV, 1×10¹⁶ cm^-2) into the buffer reduced forward-voltage drift ΔV_F by 97% at 600A/cm². The implanted diode extended the safe operating current range to 1300A/cm², ~200A/cm² higher than the reference, confirming effective suppression of bipolar degradation. Once the suppression barrier, defined as a critical excess hole density threshold, was exceeded, the proton-implanted diode exhibited explosive basal plane dislocation activity, leading to the formation of multiple bar-shaped stacking faults. These active BPDs are located deeper than the proton-implant tail, at a depth of around 11.4µm; however, the threshold hole density required for their activation remains approximately the same (~ 4×10¹⁶ cm^-3) [3].

Abstract: Ultraviolet (UV) irradiation on 4H-SiC epitaxial wafers, conducted prior to metalized circuit formation, is widely used to reveal whether BPD (basal plane dislocation) induced nucleation and expansion of a single Shockley stacking fault (1SSF) occurs or not via recombination enhanced dislocation glide (REDG). However, the UV method has remained largely qualitative, and its quantitative relationship to forward bias current injection has not been established. Here, using the excess minority carrier density at the BPD-to-TED (threading edge dislocation) conversion point, we establish equivalence criteria between two stress modes (current density and UV irradiance) and introduce a previously overlooked requirement for pulsed UV laser sources: the minority carrier density must exceed a threshold and be sustained for a finite “critical duration,” t_crit. Notably, t_crit shows only weak dependence on the bulk carrier lifetime (τ_b), offering a practical route to determine pulsed UV irradiation conditions that faithfully emulate forward bias stress, even when τ_b is unknown.

Abstract: The yield of power electronic devices is influenced by many factors including crystal defects like stacking faults (SFs). There are different types of stacking faults but their influence on the finished device and its performance and the behavior of SF during processing is not fully understood yet. With our contribution, we shed light on the issue, showing four different optically characterized subtypes of SFs with different electrical behavior that can already be found after implantation and wafer annealing in photoluminescence (UVPL) imaging. This enables a distinction between different SF classes without the need for a finally processed device and the corresponding electrical characterization. The goal of this paper is to illustrate an alternative for subdividing SF types that would otherwise be detected as triangular defects without any distinction and to show the different effects those subclasses have on finished devices with non-destructive methods that can be used in between device manufacturing steps. These results will be used as basis for further studies to confirm the found classes and to compare them with research about the different crystal structures by spectral PL measurements. For better understanding of the effect on the finished device, the PL imaging data is correlated with I-V characteristics of trenched diodes and the defect types are evaluated on their effect on the I-V characteristic, identifying 3 defect types with detrimental influence on the reverse bias and blocking voltage while the forward bias characteristic and I-V characteristic of one type is not effected by the defects.

Abstract: Bipolar degradation is a well-known issue when using body diodes in SiC-MOSFETs. Recent studies suggest that H⁺ (proton) implantation can effectively inhibit this degradation, but demonstrations on its suppression are still limited. Therefore, in this study, we have experimentally demonstrated how the expansion of Shockley-type stacking faults (SSFs) is suppressed by proton implantation. We fabricated a vertical SiC-MOSFET, in which protons were implanted into the middle depth of the drift layer. We then subjected the body diode to continuous current stress and performed photoluminescence (PL) analysis. Detailed PL image and emission spectral analysis of SSFs revealed that the proton-implanted layer can function as a recombination-enhancing layer during bipolar operation. Furthermore, it can be formed at any depth within the drift layer by controlling the energy, offering a significant advantage in the design of SiC-MOSFETs.

Abstract: 4H-SiC with 180 μm epilayer was subjected to UV exposure. Stacking fault expanded from basal plane dislocation (BPD) loop generated during growth in the epilayer was observed by UV Photoluminescence Imaging (UVPL) and X-ray Topograph (XRT) techniques. Interactions between partial dislocation, emanating from the BPD loop and gliding via recombination-enhanced dislocation glide mechanism, and threading screw/mix dislocations are detected and analyzed, where stacking faults migrate to different basal plane after the interactions. Such migration increases the faulted volume that can severely degrade reliability and performance of high power SiC devices by increasing reverse leakage current and on-state resistance and could eventually lead to device failure.

Abstract: In this paper, a method for suppressing bipolar degradation through proton implantation was investigated. Previous work suggests implantation applied to the full thickness of the epi layer, which results in unwanted defects leading to a deterioration in performance. In this work, proton implantation to the buffer layer was successful in reducing the forward-voltage drift ΔV_F of the fabricated SiC PiN diode by 85% at a current density of 800A/cm², when applying room temperature (RT) proton irradiation at a dose of 1×10¹⁶ cm^-2. Irradiation solely to the buffer layer keeps the deterioration of forward current performance to a minimum, while the fabricated SiC PiN diodes are more robust against bipolar degradation at higher current density. In addition, RT proton irradiated PiN diodes show full recovery from their bipolar degraded characteristics within 2.5 h of annealing at 350 °C under vacuum. This indicates proton irradiation alters the crystal structure for the stacking fault (SF) to “shrink” back with ease to their initial basal plane dislocations (BPD) state.

Abstract: Several defects were analyzed through the manufacturing chain along with their impact on devices. High kill rate of micropipes were seen on both Diodes and MOSFETs as expected. The purity of micropipe detection was found to be affected by the presence of inclusions. Inclusions were successfully sub-classified and separated out from micropipes, based on their location depth from the wafer surface. The effect on devices was found to relate to how deep the inclusion was located, with the ones at the surface having the biggest impact. Various sources of Stacking Faults (SFs) were reported, with Basal Plane Dislocations (BPDs) in the crystal being a major contributor. Higher local densities of BPDs were found to have a more detrimental effect. SFs were sub-classified using the wavelength of each peak. The effect of both overall SFs and each SF sub-type on devices was determined, each sub-type having different effect on the device. Various ways of mitigating the effects of defects and dislocations are demonstrated. Reducing killer defects, SF nucleation probability, and BPDs propagation by epitaxial process optimizations are shown. Resilience up to 3500A/cm² against bipolar degradation is demonstrated by using an engineered buffer layer. Process and device design optimizations show high resiliency against crystal and epi defects and dislocations, with improved yield and lower leakage.

Abstract: In this work, body diode stress has been carried out for 1700 V 25 mΩ planar SiC MOSFETs. The epitaxial wafers were mapped with Infra-Red photoluminescence (IR-PL) to determine and localize the exact number of basal plane dislocations present in the drift layers of each die. The SiC MOSFETs were then packaged in groups with individual BPD counts in different bins ranging from 0 up to more than 30 per device. Pulsed body diode measurements with high currents of 250-400 A (about 1000-1600 A/cm²) were then performed with electrical characterization before and after to check for drift in key electrical parameters. Significantly increased R_DSon was found after high current stress from about 300 A for devices with BPDs. A physical analysis of the degraded devices by backside electroluminescence show the presence of several trapezoid-shaped patterns indicating the occurrence of bipolar degradation.

Abstract: This work studies the variation of the defects density of in situ doped 3C-SiC layers during heteroepitaxial Chemical Vapour Deposition (CVD). A review on the evolution of defects density as a function of 3C-SiC grown thickness, for different N doping concentrations is offered. The doping range spanned in the experiment suits the realization of power devices.The outcome of this work provides an explanatory picture of the significant drop in stacking faults density by roughly an order of magnitude through the N doping at concentrations of the order of ~2.9×10¹⁹ cm^-3 during the growth. Conversely, N doping shows to favor the development of dislocation-like defects within the crystalline matrix. However, in few um, the crystal is able to display an effective dislocation closure mechanism, which rapidly recovers crystal quality.

Abstract: This study offers a comprehensive examination of the behavior of 3C-SiC crystals grown on 4° off-axis (100) Si substrates with different off-axis angles along <110> and <100> for N and Al doping, respectively. The investigation takes advantage of molten KOH etching to conduct an in-depth investigation of the average density and size of the SFs inside the crystal for both n- and p-type doped 3C-SiC epitaxial layers. Moreover, 3C-SiC grown on a <100> off-cut substrate was revealed to have a greater concentration of SFs due to the absence of self-annihilation along the plane (-1-10). Considering two different doping ranges suitable for IGBTs and MOSFETs development, the impact of doping and off-angle on the crystal quality, concentration, and length distribution of SFs was then investigated in order to quantify the influence of N and Al incorporation on the structural and optical characteristics of the semiconductor. It turned out that under heavy nitrogen doping (~10¹⁹ cm^-3), when the dopant concentration grew, the average length of the stacking faults (SFs) expanded while their density dropped.