Papers by Keyword: Stacking Fault

Abstract: The stacking fault formation in highly nitrogen-doped n+ 4H-SiC single crystal substrates during high temperature treatment has been investigated in terms of the surface preparation conditions of substrates. Substrates with a relatively large surface roughness showed a resistivity increase after annealing at 1100°C, which was confirmed to be caused by the formation and expansion of double Shockley-type basal plane stacking faults in the substrates. The occurrence of the stacking faults largely depended on the surface preparation conditions of the substrates, which indicates that the primary nucleation sites of stacking faults exist in the near-surface regions of substrates. In this regard, mechano-chemically polished (MCP) substrates with a minimum surface roughness (< 0.3 nm) exhibited no resistivity increase and very few stacking faults after annealing even when the nitrogen concentration of the substrates exceeded 1×1019 cm-3.

Abstract: 4H-SiC was grown on 4H-SiC (1100) substrates by sublimation boule growth, and transmission electron microscopic investigation was carried out. Two basal-plane-dislocations in the same basal plane (the BPD pair), whose dislocation line extend toward the [1100] growth direction, were observed as aligned along [0001]. The density of the BPD pairs along [0001] was in the same order with that of the stacking faults in the sample. A threading screw-dislocation was observed in between aligned BPD pairs. It is proposed that the interaction between stacking faults and threading screw-dislocations on the grown surface generates the BPD pairs. Since a high density of stacking faults is inherent to the growth on the substrates perpendicular to (0001), keeping an atomically flat grown surface is important to prevent the generation of the threading screw-dislocations, and thus to suppress the generation of the BPD pairs in case of the growth on (1100) and/or (11 2 0) substrates.

Abstract: The nucleation and expansion of Shockley stacking faults (SSFs) in 4H-SiC is known to induce an increase in the forward voltage drop (Vf) of bipolar devices such as pin diodes. However, recent annealing experiments have shown that SSFs can not only expand, but that low temperature annealing (210-7000C) induces a contraction of the SSFs that is coupled with a full and repeatable recovery of the Vf drift. Here we report that following extended periods of forward bias operation that the Vf drift of 10kV 4H-SiC pin diodes saturates, with the saturation Vf drift dropping with increasing stressing temperature. Upon reaching saturation, increases in temperature during forward bias operation at the same injection conditions also lead to a partial recovery of the Vf drift. Furthermore, the magnitude of this current-induced recovery is dependent upon the injection current, as reductions in the current cause a slower, but larger overall Vf drift recovery. All of these results clearly indicate that the current driving force models for SSF expansion are either incomplete or incorrect and that further efforts are required for a more complete understanding of SSF dynamics to be obtained.

Abstract: Defect formation in 4H-SiC(0001) and (000-1) epitaxy is investigated by grazing incidence synchrotron reflection X-ray topography and transmission electron microscopy. Frank-type faults, which are terminated by four Frank partials with a 1/4[0001] type Burgers vector with the same sign on four different basal planes, are confirmed to be formed by conversion of a 1c threading edge dislocation (TSD) in the substrate as well as simultaneous generation of a 1c TSD during epitaxy. The collation between the topography appearance and the microscopic structure and the variety of Frank faults are shown. Formation of carrot defects and threading dislocation clusters are also investigated.

Abstract: A review is presented of the current understanding of the dislocation configurations observed in PVT-grown 4H- and 6H-SiC boules and CVD-grown 4H-SiC homoepitaxial layers. In both PVT-grown boules and CVD-grown epilayers, dislocation configurations are classified according to whether they are growth dislocations, i.e., formed during growth via the replication of dislocations which thread the moving crystal growth front, or result from deformation processes (under either mechanical or electrical stress) immediately following growth, during post growth cooling, i.e., behind the crystal growth front or during device operation. Possible formation mechanisms of growth defects in the PVT grown boules, such as axial screw dislocations and threading edge dislocation walls are proposed. Similarly, possible origins of growth defect configurations in CVD-grown epilayers, such as Frank faults bounded by Frank partials, BPDs and TEDs, are also discussed. In a similar way, the origins of BPD configurations resulting from relaxation of thermal stresses during post-growth cooling of the PVT boules are discussed. Finally, the susceptibility of BPD configurations replicated into CVD grown epilayers from the substrate towards Recombination Enhanced Dislocation Glide (REDG) is discussed.

Abstract: We carried out investigations to elucidate the reasons for polytype changes in 4H. The aim was to sustain polytype stability throughout the entire process. The investigations were accompanied by studies on the formation of basal plane dislocations and their role as source for stacking faults. Several methods for the evaluation of material properties were applied to determine quality most precisely, e.g. KOH-defect-etching, optical microscopy, electron microscopy and X-ray-diffraction. We found out that several influences in growth conditions have to be controlled in a proper manner to achieve defect reduction. Based on these investigations we were able to improve our process and the crystal quality significantly. Best values for 3” 4H wafers show that EPD = 5x103 cm-2 , MPD < 0.1 cm-2 and FWHM-values < 15 arcsec can be achieved.

Abstract: In 3C-SiC MOSFETs, planar defects like anti-phase boundaries (APBs) and stacking-faults (SFs) reduce the breakdown voltage and induce leakage current. Although the planar defect density can be reduced by growing 3C-SiC on undulant-Si substrate, specific type of SFs, which expose the Si-face, remains on the (001) surface. Those SFs increase the leakage current in devices made with 3C-SiC. In order to eliminate the residual SFs, an advanced SF reduction method involving polarity conversion and homo-epitaxial growth was developed. This method is called switch-back epitaxy (SBE) and consists of the conversion of the SF surface polarity from Si-face to C-face and following homo-epitaxial growth. The reduction of the SF density in SBE 3C-SiC results in a tremendous improvement of the device performance. The combination of the achieved blocking voltage with the demonstrated high current capability indicates the potential of 3C-SiC vertical MOSFETs for high and medium power electronic applications such as electric and hybrid electric vehicle (EV/HEV) motor drives.

Abstract: Two basic processes, namely shear and shuffling of atomic planes can be considered as elementary mechanisms of displacive phase transformations. The atomistic models suitable to investigate the role of interfaces in the structural changes are tested. The many-body potentials are used for the description of interatomic forces. General displacements of atomic planes are examined, i.e. γ-surface type calculations extensively used for stacking fault and lattice dislocation analysis are applied to single plane shuffling and alternate shuffling of every other atomic plane producing in combination with homogeneous deformation the hcp structure. Similar approach considering shear type planar displacements leads to the Zener path between the bcc and fcc lattices. The effect of additional deformation required to obtain the close-packed atomic arrangements is analysed.

Abstract: Nitride-based optoelectronic devices prepared in the c orientation have been successfully introduced to the global marketplace and are changing the way we think about lighting. A part of the research interest has shifted toward nonpolar and semipolar orientations, which has the potential to broaden the scope and impact of this technology. This is because quantum-well structures prepared in nonpolar and semipolar orientations are able to suppress the quantum-confinement Stark effect, which has a negative impact on optoelectronic device performance. The lower crystal symmetry of such orientations provides spontaneously polarized light emission. Despite these attractive properties of nonpolar and semipolar orientations, the corresponding materials growth is not trivial. The present chapter discusses our efforts on growth of III-nitride materials in nonpolar and semipolar orientations and the related material properties.

Abstract: SiC fiber-reinforced SiC matrix composite (SiCf/SiC) is one of the leading candidates in ceramic materials for engineering applications due to its unique combination of properties such as high thermal conductivity, high resistance to corrosion and working conditions. Fiber-reinforced composites are materials which exhibit a significant improvement in properties like ductility in comparison to the monolithic SiC ceramic. The SiCf/SiC composite was obtained from a C/C composite precursor using convertion reaction under high temperature and controlled atmosphere. In this work, SiC phase presented the stacking faults in the structure, being not possible to calculate the unit cell size, symmetry and bond lengths but it seem equal card number 29-1129 of JCPDS.