Papers by Keyword: Stacking Fault

Abstract: As a new thinning and surface planarizing process of Silicon Carbide (SiC) wafer, we propose the completely thermal-chemical etching process; Si-vapor etching (Si-VE) technology. In this work, the effects of mechanical strength and surface step-terrace structure by Si-VE are investigated on the 4° off-axis 4H-SiC (0001) Si-face substrates. The indentation hardness of Si-VE surface is superior to the conventional chemo-mechanical polishing (CMP) surface even after epitaxial growth. The transverse strength of thinned Si-VE substrate is also superior to the conventional mechanically ground substrate. The surface step-terrace structures are observed by the low energy electron channeling contrast (LE-ECC) imaging technique. The latent scratch causes bunched step lines (BSLs) with various inhomogeneous step morphologies only on the CMP surface.

Abstract: The growth of n-type 4H-SiC crystal was performed by physical vapor transport (PVT) growth method by using nitrogen and aluminum (N-Al) co-doping. Resistivity of N-Al co-doped 4H-SiC was as low as 5.8 mΩcm. The dislocation densities of N-Al co-doped substrates were evaluated by synchrotron radiation X-ray topography (SXRT). In addition, epitaxial growth was performed on the N-Al co-doped substrates by chemical vapor deposition (CVD). No double Shockley type stacking fault was observed in the epitaxial layer.

Abstract: We investigated selective etching of SiC in molten KOH + NaOH + Na₂O₂ mixtures in application to defect analysis. Etch rate was measured as a function of etchant composition, temperature and other process variables. Optimal etching conditions were established for reliable differentiation between TSDs, TEDs, BPDs and stacking faults (SF).

Abstract: The stacking fault formation during physical vapor transport growth of heavily nitrogen-doped (mid-10¹⁹ cm⁻³) 4H-SiC crystals was investigated. Low-voltage scanning electron microscopy (LVSEM) observations detected the stacking fault formation on the (000-1) facet of heavily nitrogen-doped 4H-SiC crystals. Stacking faults showed characteristic morphologies, and atomic force microscopy (AFM) studies revealed that these morphologies of stacking faults stemmed from the interaction between surface steps and stacking faults. Based on these results, the stacking fault formation mechanism in heavily nitrogen-doped 4H-SiC crystals is discussed.

Abstract: We investigated improvement ways of to overcome these reliability issues in a 3.3 kV 4H-SiC DMOSFET. JFET doping with (i) narrow width and (ii) deeper depth than that of the p-well region successfully reduced the electric field in the gate insulator and the on-voltage simultaneously. We achieved a low Ron of 26 mΩcm² at a Vg of +15 V and 150 °C. And highly reliable chips of 0.1 Fit were also achieved both at a positive and negative gate bias of +15 V/ -8 V with MTTF of intrinsic lifetime over 20 years at 3 MV/cm. BTI characterstics both in positive and negative biases also proved reliability over 20 years. The body diode showed stable behavior under forward current operation which is suitable for an external diode-less power module.

Abstract: We present a model to explain forward voltage degradation of body diode in 4H-SiC MOSFET, and evaluate the velocity of SF expansion. First, by using in-situ photoluminescence (PL) observation, we investigated how a stacking fault (SF) expands from a basal plane dislocations (BPD) in the 4H-SiC epitaxial layer. Second, double-diffused MOSFETs were developed and measured before and after degradation. Then, the characteristics of the forward voltage degradation were modeled by a combination of PL imaging and electrical measurement, and the calculated characteristics are in good agreement with the measured ones. Finally, we tested the SiC MOSFETs under various stress conditions and evaluated the velocity of the SF expansion by calculation. This results indicate that the velocity of SF expansion increased with increasing forward current density and junction temperature.

Abstract: The effects of Al, Co, Re, and Ru on the stacking fault energy in Ni alloys were analyzed using computational thermodynamics. The effects of adding up to 5 at% Re or Ru to a Ni-15at%Co system were found to be weak at 300 °C, 700 °C, and 900 °C. However, Al addition decreased the stacking fault energy in a Ni-15at%Co-Xat%Ru system, where X = 0, 3, 5. In addition, this decrease in the stacking fault energy due to Al addition became more significant as the amount of Ru increased. Furthermore, in Ni–Co–Al–Ru alloys containing 9at%Al, the addition of 5at%Ru decreased the stacking fault energy as much as the addition of 12.5at%Co at 900 °C. The effects of Co and Ru addition on the γ/γ’ microstructure of Ni-based superalloys were also discussed.

Abstract: The influence of stacking faults (SFs) and triangular defects (TDs) on the electrical properties of 4H-SiC Schottky barrier diode (SBD) were investigated. The SF types and locations were distinguished and mapped by using room-temperature photoluminescence (PL) and optical microscope. SBDs were fabricated including the location of SF’s and TD’s. The effects of the types of defects and its area portion in the fabricated SBDs were also investigated. Based on the present data, 3C-TD has more harmful effect rather than the other SFs. The fabricated SBDs including SFs showed that increase of area portion of SF’s also resulted increase of specific on resistance of SBDs.

Abstract: Recently, a new Micro-Raman technique has been used to detect extended defects in 4H-SiC homoepitaxy. The method is based on the local increase of free carriers in undoped epitaxies (n < 10¹⁶ at/cm^-3) produced by a high power laser. The Longitudinal optical Raman mode (LO) is coupled with the electronic plasma generated by the laser pumping; such a Raman signal is sensitive to crystallographic defects that lead to trapping (or dispersion) of the free carriers which results in a loss of coupling. The monitoring of the LOPC allows determining the spatial morphology of extended defects. The results show that the detection of defects via the induced-LOPC (i-LOPC) is totally independent from the stacking fault photoluminescence signals that cover a large energy range up to 0,7eV thus allowing for a single-scan simultaneous determination of any kind of stacking fault. Also, the i-LOPC method shows the connection between the carrier concentration and the carrier lifetime for undoped film, obtaining meaningful information related to electrical properties of the film, and demonstrating that this technique is a fast, reliable and powerful method to characterize most of crystallographic defects (extended and point-like defects) in the semiconductor field.

Abstract: Eelectrically active defects in 3C–SiC are investigated by considering the structures and interactions of planar defects. An anti-phase boundary (APB) largely degrades the blocking property of semiconductor devices due to its semimetallic nature. Although APBs can be eliminated by orienting the specific polar face of 3C-SiC along a particular direction, stacking faults (SFs) cannot be eliminated due to Shockley-type partial dislocation glide. SFs with Shockley-type partial dislocations form a trapezoidal plate which expands the Si-terminated surface with increasing 3C-SiC thickness. Although the density of SFs can be reduced by counter termination, specific cross-junctions between a pair of counter SFs forms a forest dislocation, and this is regarded as an electrically active defect. This paper proposes an effective way to suppress the forest dislocations and APBs which nucleate during 3C-SiC growth.