Papers by Keyword: Step Bunching

Abstract: The growth conditions of 75 mm SiC crystals in the PVT process is varied by different methods while the temperature field is kept constant. The addition of graphite into the source material leads to the formation of an ordered step flow with step heights of 0.014 µm, while the addition of graphite into the source together with N₂ doping changes the step kinetics on the main facet, leading to very large, bunched steps of 0.17 µm. When elemental Si was added into the source material large macro steps are formed on the whole crystal surface. While the doping induced step bunching is related to the incorporation kinetics, the large steps induced in Si-rich conditions are attributed the reduction of surface energy. With the variation of the inert gas pressure the morphology of the surface is altered, similarly. Under low pressure conditions (0.2 mbar) a fine step structure evolves, while at a high pressure (40mbar) large surface steps are formed on the whole growth interface. Large surface steps are strongly impeded in their lateral motion at defects permeating the growth interface. At these sites the formation of foreign polytypes is facilitated.

Abstract: Shifts in the spatial distribution of threading dislocations in 150 mm 4H SiC wafers were examined as a response to intentional changes in both the flow of the nitrogen source gas used to control resistivity during bulk crystal growth, and the growth rate. The density of threading edge and screw dislocations was found to be more evenly distributed in wafers produced under a high-growth rate, low-resistivity process. This result corresponded to a flattening of the resistivity distribution, and a ~34% reduction in on-and off-facet resistivity differential. The effect was attributed to regularized 4H island coalescence due to modulation of step terrace width.

Abstract: In this study, we compare the electrical properties of MOS capacitors fabricated on different surface morphologies. Comparing a standard, low-roughness (<1nm), surface with one with a roughness of ~40nm, characterized by big macrosteps and large terraces. We compared the two surfaces for different thermal oxide thicknesses, ranging from d_Ox = 3.6 nm to d_Ox = 32 nm. The extracted interface state traps (D_it) shows a small, but systematic, decrease of ~10-15 % for the samples with macrosteps.

Abstract: The surface quality of epitaxial layers grown on 2° offcut substrates was improved. These substrates require a lower growth temperature and a lower C/Si ratio than their 4° offcut counterparts to suppress macro step bunching. Surface morphology, triangular defect density, and doping uniformity presented a trade-off relationship with respect to growth parameters. The implementation of a low C/Si ratio buffer layer led to a balance between surface defect density, which reached a minimum of 0.2 cm⁻², and good doping uniformity on an equivalent wafer size (150 mm). An evaluation of metal–oxide–semiconductor capacitors and Schottky barrier diodes fabricated on 2° offcut epitaxial layers showed that the quality of these epitaxial layers was satisfactory for application in devices.

Abstract: A molecular statics method has been used to examine the Ehrlich-Schwoebel (ES) barrier for an adatom of 4H-SiC to diffuse from the {0001} to the {11-20} facet. As the calculated results shown, for the C-terminated surface, the inverse ES barrier exist for the silicon adatom, which could cause the step bunching; for the Si-terminated surface, ES barrier exist for the carbon adatom, which could cause the step meandering and result in the transition of step-flow growth to 2D-nucleation growth. Simultaneously, the C-terminated surface is more stable than the Si-terminated surface, which may be one reason that the quality of film grown on the carbon facet substrate is better.

Abstract: Using a sessile drop method, investigation of the surface reconstruction of a Si-face, 4°off (0001) 4H-SiC surface in contact with pure silicon or Al-Si alloys has been carried out in the 1600-1800°C temperature range. In pure silicon and at 1600°C, the surface evolves with a two stage process: i) a fast step-bunching leading to parallel macrosteps and ii) a slower step leading equilibrium morphology, composed of (0001), (10-1n) and (01-1n) facets. Increasing the temperature to 1800°C or adding a few percents of aluminium drastically enhance the first stage, but strongly reduce the second one.

Abstract: This work reports about influence of step bunching of SiC epitaxial-wafer surface on Fowler-Nordheim (F-N) tunneling emission current of SiC-MOS capacitor. We have measured the effective barrier height (Φ_B) of SiO₂/SiC interface, and estimated the deterioration factor of the effective Φ_B on step bunching surface by calculating the local tunneling emission currents. Step bunching fluctuates the gate oxide thickness. The effective Φ_B value can be successively derived using our proposed partitioned model in which constant Φ_B value of flat surface is used. The fluctuation of the oxide film thickness results in the convergence of F-N tunneling emission currents at the thinner oxide in the MOS capacitor.

Abstract: On 4H-SiC Si-face substrates after H₂ etching, the defect with “line” feature parallel to a step as “bunched-step line” was observed. Using X-ray topography and KOH etching, we confirmed that the bunched-step line originated from basal plane dislocation (BPD). Use of the substrate with the lowest BPD density will be effective to reduce bunched-step line that would affect oxide layer reliability on an epitaxial layer. However, more detail investigation needs to classify the BPD that would become a starting point of bunched-step line.

Abstract: The off-axis solution growth of 4H-SiC was studied focusing on the morphological instabilities by using conventional TSSG technique. The morphology depends strongly on the crystalline polarity, and that on Si surface can be characterized by wandering while that on C surface is characterized by strong step-bunching. By raising the temperature gradient, step bunching on Si surface is considerably suppressed which can be consistent to the constitutional super cooling scheme. However, C surface exhibits strong step bunching as the temperature gradient increase. These behaviors can be explained by the difference in Ehrlich-Schwoebel barrier and diffusion behavior of adatoms.

Abstract: This work reports about effect of SiC epitaxial-wafer surface planarization by chemo-mechanical polishing (CMP) treatment on electrical properties of SiC-MOS capacitor. We have observed the surface morphology of 4H-SiC epitaxial layer planarized by CMP treatment using a confocal differential interference microscope, and evaluated the reliability of gate oxides on this surface using constant current time-dependent dielectric breakdown (CC-TDDB) and current-voltage (I-V) characteristics. Surface roughness such as step bunching deteriorates drastically the reliability of gate oxide, while the epitaxial-surface planarization by CMP treatment improved oxide reliability due to the high uniformity of the oxide film thickness.