Papers by Keyword: Sub-Surface Damage

Abstract: We have developed a novel, material-lossless silicon carbide (SiC) wafer manufacturing process that eliminates the need for conventional grinding and polishing. Utilizing a thermal sublimation growth and etching technique called Dynamic AGE-ing^® (DA), we simultaneously performed thermal sublimation etching and growth on both the Si-face and C-face of single-crystal SiC wafers. This study investigated the impact of surface undulations—arising during DA planarization of as-sliced wafers with varying slicing qualities—on the densities of basal plane dislocations (BPDs) and in-grown stacking faults (IGSFs) in the epitaxial layers. Our findings demonstrate that larger pre-growth surface undulations correlate with higher BPD and IGSF densities in the DA-grown layers. By optimizing the initial wafer quality and DA process conditions, we achieved epitaxial layers with low defect densities (BPD density of 0.09 cm⁻² and IGSF density of 1.37 cm⁻²) without any material loss. This advancement offers a significant breakthrough in SiC device manufacturing, potentially reducing material costs and enhancing device performance by suppressing killer defects in the epitaxial layers.

Abstract: In this study, we developed two planarization mechanisms, macroscopic and microscopic, controlled by adjusting the C/Si ratio during Dynamic AGE-ing^® (DA) sublimation etching. Using these mechanisms, we planarized rough 4H-SiC wafers without the use of chemical mechanical polishing (CMP). Macro planarization forms macro step bunching (MSB) using high C/Si ratio DA etching, straightens the steps using step tension, and removes scratch marks caused by mechanical processing. Microscopic planarization involves debunching these MSBs using low C/Si ratio DA etching. It was observed that debunching progressed more quickly on wafers before CMP finishing due to the higher density of MSBs with ramified structures, which serve as starting points for debunching. The rate at which the MSB is shortened by step debunching increases with rising temperature, reaching about 20 μm/min at 1800 °C. By utilizing these mechanisms, we achieved high-quality planarization (initial Ra = 0.6 nm) to Ra = 0.18 nm for φ6-inch 4H-SiC wafers that had not undergone CMP. Furthermore, by performing DA sublimation growth on this planarized wafer, we achieved an in-grown stacking fault (IGSF) density of 0.09 cm⁻² and a basal plane dislocation (BPD) to threading edge dislocation (TED) conversion ratio of 99.95 %.

Abstract: We have demonstrated a novel process that precisely controls the wafer bow, a key parameter of overall warpage, of 4H-SiC wafers to any desired value by integrating a thermal sublimation process, Dynamic AGE-ing® (DA), immediately prior to the CVD epitaxial process. This method achieves atomic-level flatness of the CMP-finished surface independent of the growth and etching amounts, while concurrently eliminating sub-surface damage (SSD). When DA is applied to simultaneously etch the Si-face and grow the C-face, the wafer bow decreases linearly with increasing C-face growth. In wafers with poorer mechanical processing quality, an increase in bow is observed for C-face growth below 120 nm, likely due to the relaxation of SSD on that side. The process also removes SSD from the Si-face, ensuring that both sides are sufficiently cleared of damage. Furthermore, for wafers with an initially negative bow, simultaneous Si-face growth and C-face etching using DA produces a linear increase in bow. By applying these processes, we successfully adjusted the bow to –0.4 µm on an 8-inch wafer that initially measured –12.0 µm. These results indicate that, regardless of the initial bow severity, precise control of the wafer bow can be achieved without adversely affecting subsequent CVD epitaxy processes by appropriately managing the growth layer thicknesses on both faces using DA.

Abstract: The modified SiC slurry for CMP process was proposed in order to obtain high-quality surface of 150 mm SiC wafer and then tried to explain the mechanism of the effect of added transition metal ion to improve polishing characteristics of SiC crystal substrate. SiC substrate with using modified slurry exhibited slightly higher MRR value and lower platen temperature than those with using commercial slurries. The addition of transition metal ion into the slurry enhanced oxidation efficiency of SiC crystal surface and improved MRR and the quality of SiC surface.

Abstract: In conventional machining of SiC wafers, material loss and sub-surface damage (SSD) of both the front and back surfaces are major issues. In this study, we focused on Dynamic AGE-ing^® (DA), which is a sublimation-controlled process, and applied it to the total wafering process without any mechanical contact of both the front and back surfaces to explore the possibilities to reach the CMP-equivalent quality. DA process enables material lossless planarization of SiC wafers by applying a temperature gradient to achieve simultaneous etching and growth at the same rate on one and the other surfaces, respectively. To drive the planarization function for a multi-wire saw finished as-sliced wafer, as an example, a high-temperature regime above 2000 °C under an Ar background pressure higher than 1 kPa to suppress etching and growth rates was employed as the first step in the DA treatment. In this step, an effective annealing function arises where sublimation and recrystallization occur simultaneously through a sub-surface region on both sides of the wafer. Due to the active interchange of the surface and subsurface layer, a self-organizing planarization effect occurs on a macroscopic scale on both surfaces with the removal of SSD. The conventional DA processes were employed for the following microscopic flatness control. As a result, the roughness of the 6-inch as-sliced wafer was reduced to 0.7 nm on the Si-face and 2.0 nm on the C-face while maintaining the wafer thickness. This is the first promising result exhibiting the potential of thermal contactless treatment for next-generation wafer manufacturing by improving quality and cost.

Abstract: Developing an observation method for distributing sub-surface damage (SSD) on large-diameter 4H-SiC bulk wafers formed by mechanical processing can significantly improve the epitaxial and bulk growth processes. This study used a novel laser light scattering (LLS) technique to observe SSD distribution on a 6-inch 4H-SiC (0001) wafer. As a result, scattering intensity distributions similar to the grinding and lap-polishing traces and the shape of the jig used to hold the wafer during polishing were observed on the CMP-finished SiC wafer surface. Since the surface topography of the area was flat by a laser microscopy observation, it is assumed that this is the SSD. This result suggests that LLS can be a wafer inspection method that can observe SSD distribution. In addition, wafer inspection using LLS has demonstrated that it is possible to observe scratches, particles, and macrostep bunching. This method is anticipated to allow further optimization of the mechanical processing and thermal etching process prior to CVD epitaxial growth.

Abstract: Improving the visibility of defects in nitrogen-doped 4H-SiC (0001) bare wafers by photoluminescence imaging (PLI) is essential for improving the epitaxial growth process and device yields. This study proposes sub-surface damage (SSD) introduced during the mechanical process of SiC wafers as a new factor in reducing defect visibility in PL images. To verify the effect of SSD, we observed the surface of a SiC wafer, which was thermally etched at about 3 μm. As a result, dramatic defect visibility improvement was observed when the surface roughness was sufficiently flat (Ra < 0.3 nm) after thermal etching. Thus, the results suggest that defect visibility in PL images can be improved by controlling SSD and surface roughness. Using the background noise reduction effect of the SSD removal, not only PLI but also many other wafer surface inspections are expected to be improved.

Abstract: 4H-SiC surfaces before and after epitaxial growth (substrate and epitaxial layer surfaces) were investigated by mirror projection electron microscopy (MPJ) and atomic force microscopy (AFM). On the epitaxial layer surface, two types of short-step-bunchings (SSBs) were observed, one of which featured double grooves and protrusion perpendicular to the step-flow direction and the other, a single groove and protrusion. We also investigated the substrate surface and detected features of sub-surface damage and dislocations. These surfaces were compared and the relationship between the SSBs on the epitaxial layer surface and sub-surface damages and dislocations on the substrate surface were discussed.

Abstract: The impact of surface stress due to polish and grind processes on wafer bow was studied as a function of abrasive size. Results indicate that sub-surface damage from these processes can introduce significant surface stress. For polishing processes, this stress is proportional to mean abrasive size. The study also investigates stress as a function of depth below the wafer surface and finds that most stress is concentrated near the wafer surface.

Abstract: The flatness of a silicon carbide wafer in terms of bow and warp is the result of the combination of factors both material and process related. Sub-surface damage (SSD) from the wafering process steps can be considered as a thin film under compressive stress on the wafer surface. SSD is generally decreased with each subsequent processing step after the multiwire saw. Single-sided process steps can produce very different levels of SSD on opposing wafer surfaces, leading to high bow and warp values. The present study investigates the effects of SSD on wafer flatness at various process steps as well as methods to minimize shape effects due to SSD during and after processing.