Papers by Keyword: Surface Potential

Abstract: Abstract. Advanced semiconductor technology features complicated three-dimensional nanostructures and nanoconfined spaces such as nanosheets, supervias, deep contact holes and nanocavities. Uniform wet etching of such nanoconfined spaces across different feature sizes or critical dimensions (CD) is extremely challenging. Typically, etch rate decreases with decrease in CD size. In this paper we report methods to achieve uniform wet etch rate (ER) of SiO₂ across different CD sizes by mixing organic solvents in the etching solution. We also report a reversal of etch rate trend where SiO₂ structure of smaller CD etches faster than a larger CD, by tuning the ratio of organic to water solvents in the etching solution. We also investigate the impact of parameters such as solvent type, wall material, surface tension and ionic strength on ER. Our data suggests, while surface tension and ionic strength show no impact, the type of wall material, surface potential and organic solvent amount in the etching solution show a strong influence on SiO₂ ER. Also, zeta potential could explain most of our results but not all, suggesting that surface potential is not the only factor impacting CD dependent ER in a nanoconfined spaces.

Abstract: Wet etching in nanometer-sized three-dimensional spaces creates new challengesbecause of the scaling of semiconductor devices with complex 3D architecture. Wet etching withinspaces is affected by the mass transport of the etchant ions that are impacted by the hydrophobicityand surface potential of surface. However, the kinetics of chemical reactions within the spaces is stillunclear.In this paper, we studied the effect of hydrophobicity and surface potential of silicon surface on SiO2etching in nanometer-sized narrow spaces by adding various additive components to etching solutions.We found that the transport of etchant ions into narrow spaces is governed by controlling thehydrophobicity and surface potential of the confined system walls.

Abstract: During low-temperature annealing, the segregation of the alloying element leads to a strong enrichment of the surface layer, causing a rearrangement of the surface electron structure. This change in the electron structure is manifested in the characteristic energy loss spectra. Annealing of single crystals at 400–500 K leads to an increase in the density of surface electron states. As shown by the calculations of the surface potential using experimental data on the temperature dependence of the surface concentration, dopant segregation causes a linear increase in the surface potential.

Abstract: In this work, we have analyzed the digital and analog performance for InGaAs/InP heterojunction Gate all around MOS structure. A detailed study on the impact of Barrier thickness on different analog and digital performance for an InGaAs/InP hetero structure GAA MOSFET is carried out by using TCAD device simulation. The electrical parameters such as surface potential, electric field, transfer characteristics, output characteristics, transconductance and output conductance is carried out and analyzed by varying the barrier thickness from 1 nm to 4 nm. Based on the simulation results it is investigated that the effect of the all electrical parameters in the nanoscale devices. It has been seen from the presented results that the influence of barrier thickness variation gives the notable improvement in drain current. The impact of InGaAs/InP hetero structure and barrier thickness variation claims GAA MOSFET as a promising candidate for VLSI applications. Keywords: Heterojunction, InGaAs/InP, TCAD, Analog parameters.

Abstract: In this paper, an analytical model for modified Surrounding Gate Tunnel FET with gate stack engineering and different gate metals has been developed. Further, considering the scaling advantageous of Gate stack engineering and high degree performance of dual material engineering, the both has been integrated into a novel structure known as Surrounding Gate (SG) Tunnel FET with stacked oxide SiO₂/high-k and dual material (DM) has been proposed. The two dimensional (2D) potential at the surface and electric field mathematical models for the DMSG TFET are developed by solving 2D Poisson's equation with matching device boundary conditions. Based on the Kane's formula, mathematical expression for the band-to-band (BTB) tunneling generation rate is derived and then used to calculate the drain current. The impact on the proposed device performance due to the variation of different device parameters has also been studied. It has been found from the presented results that the ON current of the DMSG TFET with stack is 10^-6A, OFF current is 10^-13A and ON/OFF ratio is 10⁷. The mathematical results have been verified using the simulated results obtained from TCAD, a 3-D device simulator from ATLAS.

Abstract: In this paper, a comparative analysis of the Tri-gate MOSFET device structure with respect to Single Material Gate (SMG) Tri-gate MOSFET, Double Material Gate (DMG) Tri-gate MOSFET and Triple Material Gate (TMG) Tri-gate MOSFET with & without Hafnium dioxide as high-K dielectric material is employed using Silvaco TCAD Atlas Tool. It shows a compact model and better DC, AC performance for triple material gate structures and yields a high drive current of the device for TMG Tri-gate MOSFET with high-k dielectrics and shows a better electrical characteristics in comparison with other device structures.

Abstract: This paper describes the analytical modeling and simulation of Triple Material Double Gate Metal Oxide Semiconductor Field Effect Transistor (TMDG MOSFET) with no junctions. Three kind of gate materials with different work function values over the channel helps to improve the ON current and to form a barrier in the channel helps to reduce OFF current. It has been found from the obtained results that the OFF current or leakage current of the device is exactly low (I_OFF =10^-11 A) which is fit for low power applications. Also, the extracted value of I_ON current (10^-3 A) has proved that there is a remarkable improvement with decreasing device dimensions. The overall gate length (L), work functions of gate materials, oxide thickness (t_ox), silicon thickness (t_si) and doping concentration (N_d) are optimized at 60nm, 4.8eV, 4.6eV, 4.4eV, 1nm, 10nm and 10¹⁹ cm^-3 respectively. The 2-D Poisson equation has been solved by using parabolic approximation technique to obtain the potential distribution function in the channel. Based on this expression, analytical models of the lateral electric field, subthreshold slope and drain current for Junctionless Triple Material Double Gate Metal oxide semiconductor Field Effect Transistor (JL TMDG MOSFET) were derived. Finally, the validity of the proposed analytical model is compared with numerical solution simulation data results which are obtained by using TCAD device simulator.

Abstract: In this paper, we propose the analytical modeling for fully depleted surrounding gate TFET surrounding gate tunneling field effect transistor with single metal gate. This model comprises the surface potential using 2-D Poisson’s equation and drain current with the effects of oxide thickness, silicon thickness as radius, drain voltage, gate metal work function, and assuming channel is fully depleted. The model is tested using TCAD Simulation Tool.

Abstract: MC3T3-E1 cell differentiation and related surface potentials of rutile-type TiO₂ scales formed on Ti are controlled by varying the Ti heat treatment conditions in a N₂ atmosphere containing a trace amount of O₂. The zeta potentials of the samples heated at 873 and 973 K for 1 h show large negative and positive values, respectively, while cell differentiation on the surface is enhanced in both cases (14 days incubation). In the case of untreated Ti, the cell differentiation diminishes and the zeta potential becomes more neutral. Protein detection by an immunogold-labeling technique and Ca and P detection by time-of-flight secondary ion mass spectrometry reveal that Ca and P, rather than an adhesive protein such as fibronectin, predominantly adsorbed on the scales formed in 1 h at 873 and 973 K, respectively. In the case of untreated Ti, both fibronectin and a non-adhesive protein such as albumin adsorbed, but no Ca and P were detected. The present findings illuminate the relationship between charged surfaces and MC3T3-E1 cellular response.

Abstract: We build up the electrostatic model for Triple Material Quadruple Gate (TMQG) Tunnel Field Effect Transistor of rectangular cross area, in view of semi 3D strategy in this paper. The Parabolic approximation method is utilized to tackle the 2-D Poisson condition with appropriate device boundary conditions and logical articulations for surface potential and electric fields are determined. The electric field dispersion is additionally used to ascertain the tunneling generation rate. The created show furnishes the plan rules of TMQG with enhanced I_ON current. The diagnostic outcomes are contrasted and TCAD recreation comes about.