Papers by Keyword: Switch

Abstract: This paper analyzes the performance indicators multiservice telecommunication networks based on the future network architectural concept using end-to-end digital technologies. Based on the study, a new approach to constructing a mathematical model of the efficiency of an SDN network is proposed. Based on the model, analytical expressions were obtained to evaluate the performance switches and controllers of the software defined networking network using the OpenFlow protocols.

Abstract: A family of planar MOSFETs with voltage ratings from 900 V to 15 kV are demonstrated. This family of planar MOSFETs represents Cree’s next generation MOSFET design and process, in which we continue to refine and evolve device design and processing to further shrink die sizes and enhance device performance. At voltage ratings of 3.3 kV and above, the specific on-resistance of the MOSFETs is approaching the theoretical limit. MOSFET switching performance in a clamped inductive switching circuit for the full range of voltage ratings is also demonstrated. Finally, improved threshold voltage and body diode stability under long-term stresses are presented.

Abstract: As the basis for comprehensive integration of the aircraft, AFDX network has been widely used in avionics network. AFDX’s reliability analysis and verification is particularly important according to the requirements of airworthiness. The transmission process, components and functional contact between components of AFDX network is analyzed in this paper. Dynamic fault tree (DFT) is used to model AFDX network reliability according to network fault characteristics. This analysis process has two contributions for network reliability analysis. Firstly, the analysis of AFDX network failures is implemented to device-level, which is facilitated to quantitative calculations in engineering. Secondly, end system and switch system, the core subsystem in transmission of AFDX, are analyzed and modeled, besides fault of redundant network.

Abstract: Recently, we proposed an innovative switch architecture called Contention-Tolerant Crossbar (CTC) switch. It is able to tolerate conflicts in switch fabric. The schedulers of CTC are distributed in inputs and operate independently and in parallel, which releases the central controller and cooperative arbiters, and largely reduces the hardware complexity. In this paper, we discuss a general model by discussing a CTC structure with X inputs and Y outputs called (X, Y)-CTC Structure. And a queueing network model is developed for analyzing the throughput of this general structure. Since it has the main characteristics of CTC, it can be seen as the basis of modularity study of Contention-Tolerant Switches.

Abstract: A capacitor memory erasing technique for pipeline ADC is introduced, which insert a clearing phase to the traditional working timing sequence of the MDAC to erasing the residual charges on the sampling capacitor. The measurement shows that the 14-bit pipeline ADC adopting the proposed technique can achieve a sampling rate of 250MSPS with SNR 69dB, SFDR 80dB, compared with the traditional ADC of sampling rate 100MSPS, SNR 60dB, SFDR 71dB, which proves the proposed technique can improve the performances of pipeline ADCS obviously.

Abstract: The urban area of the server can be a central control node switch and server node, the node switches and a server node can know the porttraffic information in real time. When the connection existed over between 2 of these devices, a connection can be selected according to the real-time traffic, real-time routing function to avoid network congestion and flow of the uneven distribution of resources. Similarly, node server can central control node switch can know the real-time node switch port flow information, therefore, the node switches can obtain the terminal flow control information from the server to the terminal node data transmission flow control.

Abstract: In contrast to the Moore’s Law exponential growth in CMOS transistor areal density, computer clock speeds have been frozen since 2003 due to excessive power dissipation. We present the development of a new digital switch, the PiezoElectronic Transistor (PET), designed to circumvent the speed and power limitations of the CMOS transistor. The PET operates on a novel principle: an electrical input is transduced into an acoustic pulse by a piezoelectric (PE) actuator, which, in turn, drives a continuous insulator-to-metal transition in a piezoresistive (PR) channel, thus switching on the device. Predictions of theory and simulation, assuming bulk materials properties can be approximately retained at scale, are that PETs can operate at one-tenth the present voltage of CMOS technology and 100 times less power, while running at multi-GHz clock speeds. CMOS-like computer architectures, such as a simulated adder, can be fully implemented. Materials development for PE and PR thin films approaching the properties of bulk single crystals, and a successful fabrication scheme, are the key to realizing this agenda. We describe progress in developing PE films (where d₃₃ is critical) and PR films (characterized by conductance and ON/OFF ratio) of demonstration quality. A macroscopic-scale PET has been built to demonstrate PET viability over large numbers of switching cycles. The perspective for the development of pressure-driven electronics will be outlined.

Abstract: In order to improve network reliability and stability of the core layer, multiple devices are connected together through the IRF physical port, IRF (Intelligent Resilient Framework) configuration, virtual into “virtual equipment”. Using the virtualization technology can set the equipment resources of the hardware and software processing capability, collaborative work, the equipment management and the uninterrupted maintenance. Through introduce the basic concepts and working principles of H3C Switches IRF system, also analyzes the typical applications of IRF technology in network system.

Abstract: ‘SIM’ is the abstraction of ATM Switching Architecture Simulator which is developed by Stanford University based on time-slot. It’s produced to simulate ATM network. With the SIM, users can simulate the ATM switchboard in accordance with their needs on Linux platform. Multi-core CPU programming technology enable programs parallelized and achieve high improvement on performance. Therefore we bring this idea to develop a parallelized switch simulator called PSIM in this paper.

Abstract: this paper mainly introduces a wideband SPDT switch with TTL control. Firstly, everypossible configuration is contrasted, the theories of basic GaAs switch configurations arementioned. Secondly, the theories of basic GaAs switch configurations are mentioned.Subsequently, appropriate topology is selected for this SPDT switch. This switch has been realizedby 0.5µm GaAs pHEMT process. this switch exhibits high performance: over DC~4GHz, insertionloss is lower than 1dB; The isolation is lower than 50dB; the ripple variation of insertion loss is lessthan ±0.15dB; input return loss is lower than 14dB; on state, output return loss is lower than 16dB;off state, over 0.2GHz-4GHz, output return loss is lower than 12dB; on and off time are less than55ns. The layout of the switch with a chip size is 0.81 mm×1.22mm.