Papers by Keyword: TDDB

Abstract: In this paper, we study high-temperature H₂, N₂, and H₂/N₂ surface conditioning processes prior to the SiO₂ deposition as a promising approach for SiO₂/4H-SiC interface preparation in metal-oxide-semiconductor field-effect transistors (MOSFET). A thorough electrical analysis is presented, consisting of temperature-dependent transfer characteristics as well as reliability studies regarding bias temperature instabilities (BTI) and dielectric breakdown behavior. Especially N₂-containing surface pretreatments were found to greatly suppress electron traps, whereas hole trapping is enhanced. Finally, X-ray photoelectron spectroscopy (XPS) was utilized to elucidate the elemental surface composition after the different annealing procedures. The obtained results are in good agreement with the electrical characterization and complement already published results regarding the formation of surface reconstructions on 4H-SiC through H₂ and H₂/N₂ annealings.

Abstract: In this work, a comparison of standard bulk 4H-SiC epi wafers and Soitec's SmartSiC™ wafers as well as the influence of RTA processing was conducted. For this, MOS capacitors were processed using thermal gate oxide paired with a polycrystalline gate electrode. Subsequent High temperature steps were avoided until an RTA process was performed on some of these wafers. To investigate the oxide quality on all wafer and process splits, CV-, time-zero dielectric breakdown and constant-current stress time-dependent dielectric breakdown measurements were carried out. For the examination of bulk wafers and SmartSiC™, no relevant differences in terms of yield, oxide quality, interface state density and reliability were found. In contrast, RTA processes seem to create a shift in flat band voltage and also lead to a reduction in oxide lifetime. The V_FB shift could partially, but not completely, be explained by addition activation of dopants in the polysilicon electrode. The influence on the oxide reliability, however, is still unclear.

Abstract: In this paper, 1.2 kV SiC trench MOSFET with deep P structure has been proposed to effectively shield the trench bottom oxide. The various design splits, such as N concentration between deep P and deep P to trench distance, were experimentally evaluated and TCAD simulations were performed to extract maximum oxide electric field at trench bottom. Based on trade off results, critical design parameters were optimized to obtain low Rdson and stable breakdown voltage with acceptable oxide electric field. To evaluate trench gate oxide reliability in wafer level, gate oxide integrity (GOI/Vramp), charge to breakdown (QBD), and time dependent dielectric breakdown (TDDB) tests were conducted. Also, high temperature gate bias (HTGB) and high temperature reverse bias (HTRB) stress tests were carried out for assembled samples to compare device reliability depending on different designs. For the target design, the promising reliability results were confirmed in both wafer level and assembled samples.

Abstract: We report an AEC-Q101-qualified 750V, 15 mΩ planar SiC MOSFETs with a long short circuit withstand time (SCWT) of > 9μs at V_DS=400V and V_GS=15V and a low specific on-resistance (R_ON,SP) of 2.1 mΩ.cm² at V_GS=15V designed for xEV traction inverter applications. The R_DS(on) at V_GS=15V increases from 15mΩ at 25 °C to 21 mΩ at 175 °C. A low turn-on (E_ON) and turn-off (E_OFF) switching energy loss of 95.5μJ and 67μJ at I_DS=75A, V_DS=400V was measured at 25 °C. The gate oxide lifetime at worst case operating fields of 5MV/cm is >> 20 years.

Abstract: A systematic capacitance-voltage (C-V) and time-dependent dielectric breakdown (TDDB) study on silicon carbide (SiC) metal-oxide-semiconductor capacitors (MOSCAPs) that use silicon dioxide (SiO₂) is shown in this paper. Oxides were formed using atomic layer deposition (ALD), low-pressure chemical vapour deposition (LPCVD) or direct thermal growth in nitrous oxide (N₂O) ambient, where both deposited oxides were post-deposition annealed in N₂O ambient, too. The electrical characterisation results reveal that the ALD-deposited and N₂O-annealed oxides show the best capacitance-voltage (C-V) characteristics, with flatband and hysteresis voltages (V_FB) averaging 1.44 V and 0.41 V, respectively. When measuring the leakage current levels at 175°C, the ALD-deposited MOSCAPs’ breakdown electric fields are averaging similar to their counterparts at 9.71 MV/cm. MOSCAPs which utilized ALD-deposited SiO₂ also showed 29% and 345% increased average injected charge-to 63% failure (Q_BD,63%) at 9 MV/cm and 9.6 MV/cm, respectively, when comparing these devices to their direct thermally grown SiO2 counterparts.

Abstract: Power devices are susceptible to failure by terrestrial neutron single-event burnout (SEB) while in the high-voltage blocking state and above a V_DS threshold for that device. Typically, the SEB failure rate is measured at a high blocking voltage, with the source and gate at ground potential. Here the effect of a negative gate bias, commonly applied during MOSFET switching to the blocking state, on the SEB failure rate is examined. It is observed that the SEB failure rate is only weakly dependent on the negative gate bias, because it does not significantly affect the peak field in the drift region where avalanche breakdown is initiated. A negative gate bias of -8V_GS in the device blocking state at 1100V_DS only results in a 6% increase in the MOSFET SEB failure rate.

Abstract: We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

Abstract: A systematic post-deposition annealing study on Silicon Carbide (SiC) metal-oxide-semiconductor capacitors (MOSCAPs) using atomic layer deposition (ALD)-deposited silicon dioxide (SiO₂) layers was carried out. Anneals were done in oxidising (N₂O), inert (Ar) and reducing (H₂:N₂) ambients at elevated temperatures from 900°C to 1300°C for 1 hour. Electrical characterisation results show that the forming gas treatment at 1100°C reduces the flatband voltage to 0.23 V from 10 V for as-deposited SiO2 layers. The density of interface traps (D_IT) was also reduced by one order of magnitude to 2×10¹¹ cm^-2 eV^-1 at E_C-E_T = 0.2 eV. As an indicator of the improvement, characterisation by x-ray photoelectron spectroscopy (XPS) showed that silicon enrichment present in as-deposited layers was largely reduced by the forming gas anneal, improving the stoichiometry. Time-dependent dielectric breakdown (TDDB) results showed that the majority of forming gas annealed samples broke down at breakdown fields of 12.5 MV × cm^-1, which is about 2.5 MV × cm^-1 higher than for thermally oxidised samples.

Abstract: We used the POCl₃ gate technique for the fabrication of 4H-SiC vertical MOSFETs, and examined its effect on the V_TH-R_ON tradeoff and the compatibility with device fabrication. The gate oxide film was formed by thermal dry O₂ oxidation followed by POCl₃ or NO annealing. The POCl₃ process reduced R_ON by about 30% compared with the NO process for the ones having V_TH of 1.1 V, being attributed to the channel mobility enhancement. Moreover, the improvement was more effective for higher V_TH designs. The conventional thermal treatment after the gate process considerably spoiled the channel mobility improvement brought by the POCl₃ annealing and strengthened negative charge trapping in the gate oxide. The presumed extra-formed defects also affected the E_OX dependence of t_BD on the TDDB tests, being expected to shorten the gate oxide lifetime under practical device operation stress. Successful insertion of the POCl₃ process into production lines depends upon careful low-temperature post processing.

Abstract: Gate oxide reliability on silicon carbide MOSFETs and large-area SiC N-type capacitors was studied for devices fabricated on 150mm SiC substrates. Oxide lifetime was measured under accelerated stress conditions using constant-voltage time-dependent dielectric breakdown (TDDB) testing, or ramped-voltage breakdown (RBD) testing. TDDB results from 1200V Gen3 MOSFETs reveal a field acceleration parameter of about 35 nm/V, similar to values reported for SiO₂ on silicon. Temperature-dependent RBD tests of large capacitors from 25°C to 200°C reveal an apparent activation energy of 0.24eV, indicating that oxide lifetime increases as the temperature is decreased, as expected. Using this acceleration parameter and activation energy in the linear field model, the gate oxide lifetime from MOSFET TDDB testing extrapolates to greater than 10⁸ hours at a gate voltage of 15 V_GS at 175°C.